Are you seeing UI shrinkage?

High-speed signals are susceptible to signal-integrity issues because they involve very fast edges and very narrow UIs (unit intervals) or bit times. As the data rate for a PHY communication link increases, two things happen: The UI narrows and the rise time of the signal decreases. For example, when comparing a 5 Gb/s pulse with an 8 Gb/s pulse, the UI width drops dramatically from 200 ps to 125 ps. The result is 38% less margin (that is, error budget) in a design. This situation makes the task of the receiver even tougher as it tries to distinguish a “1” from a “0” at very fast data rates with little room for error in its logical interpretation. Rise time also decreases from about 30 ps to just over 28 ps. Check out the 8 Gb/s measurement I made on a DPO72004 scope in my lab—a 28 ps rise time!

Complicating the issue is the fact that multiple signal-integrity issues can be introduced as a transmitted signal—one with a very small UI—makes its way to the receiver. These signal-integrity issues can include attenuation as the signal travels across a circuit board or from the Si die to the package pins and onto the circuit board. Attenuation in a channel is a serious issue that must be addressed. Losses in PCB material such as FR-4 increase with trace length as well as with data rate. As signal amplitude shrinks, noise and reflections are becoming a bigger factor.

Are you seeing shrinkage in your lab? If so, how are you dealing with it?