Signal access, timing analysis drive faster DDR memory-system debug

The ramp-up in memory-system speed and capacity over the past few years has been incredible and has opened the door for a greater role for DRAM in computer systems. Capacities in the hundreds of gigabytes are becoming commonplace in high-end servers, and high-speed memories are now being asked to lighten the burden on CPUs for memory-intensive tasks.

With this speed increase comes challenges for verification of performance levels as specified by JEDEC (Joint Electron Device Engineering Committee). Because of the complexity inherent in the JEDEC-specified measurement methods, reference levels, pass/fail limits, etc., it is very useful to have an application-specific measurement approach for memory-system testing.

One of the first obstacles to overcome in memory validation is the issue of accessing and acquiring the necessary signals. JEDEC specifies that electrical measurements should be made at the BGA ballouts of the memory component. Most components have ballouts that, for practical purposes, are physically inaccessible, so there are two main approaches:

1. Plan ahead by placing vias directly on memory-system PCBs during layout. Access to these vias for test points will be physically close to the operational ballouts to ensure good signal representation for your testing. However, these vias will most likely be very closely placed, so plan to use an oscilloscope’s solder-down probing system to enable tight-fit, high-signal-fidelity test points to be put in place. This webinar is a good resource.
2. Place an interposer into your memory-system test setup so you can access signal properties without disturbing the PCB layout. Memory-system interposers use a socket that solders down onto the device under test in place of the memory component. The interposer, which has test points for probing, then snaps into place on the socket. The memory component attaches to the top of the interposer. This setup puts the system access right between the DRAM and the memory controller.

Once signals are accessible, the next challenge is to assess digital timing performance according to JEDEC specs. Capturing and evaluating read-writes can be difficult when the timing envelope is in the picosecond range. One of the simplest methods is to use the DQS (data qualifier signal) or data strobe signal to identify the start of a read or write burst. Oscilloscope hardware triggering capabilities can trigger on this start portion of the burst and assure that only reads or writes are captured at the beginning of the acquired waveform.

Beyond hardware triggering, new visual triggers allow for custom-designed shapes for more versatile DQS burst capture capability. Visual Trigger lets users place custom-designed shapes directly on the scope’s display where the boundaries of the shape define trigger events for a DQS or data strobe being acquired. These shapes can be moved, rotated, and modified into one of four different shapes (for example, triangle or trapezoid) on the scope graticule and can be combined with traditional scope trigger functions to enable a more comprehensive and accurate memory-system signal capture.

How are you coping with the ever-increasing demand for faster memories with higher capacities and lower costs? What else could those of us in the test-and-measurement industry be doing to help?