Don’t be like Tiger—Keep your serial buses out of contention
After a long and highly public dry spell, Tiger Woods is back in contention with his first tournament win in two years. For Tiger, being in contention is a very good thing.For electrical designers working on high-speed serial buses, however, contention is very bad thing. The outcome is not win-win when your memory modules or A/D converters and I/O devices engage in mortal combat for control of the bus.
This contention is a great example of how serial buses are more difficult to debug than parallel buses. The serial bus depicted below is the I2C bus standard layer and protocol developed by Philips Semiconductor. The diagram shows various connected devices, each selected by a unique address identifier contained in each serial packet transmitted.
Most digital oscilloscopes will trigger on logic signal combinations described as either pattern or state signals. The screen capture below illustrates how engineers have had to decode I2C serial buses, bit by bit-first finding the Start of Packet transition; then identifying the address, which is the first seven bits of the first byte; and then looking at the eighth bit of the first byte to determine if it is a read or a write and decoding the data up to eight bytes. In the image below, the address is 76; the operation is a read.
Some serial buses, like CAN bus, are impossible to decode by hand because of bit correction. Many oscilloscopes today provide I2C, SPI, and CAN bus triggers that permit debugging bus contention by triggering on signals specific to these buses at rates up to 10 Mbps. Using these triggers makes it easier to set up expected bus patterns. For example, on an I2C bus you might want to trigger on the start or end of a packet, the type of frame (data, remote, error, or overload), a standard or extended identifier, or even a missing acknowledgment.
With serial bus triggers, searching for and triggering on common packet information can be done more quickly, as shown below. In this case, an oscilloscope is set up with an I2C bus to trigger on the selected address, 76, for a read or a write. Each packet is easily decoded, eliminating hand decoding, reducing errors, and saving time.
What techniques and tricks are you using to find and eliminate contention in your serial-bus designs?
Larry M commented:
On the first diagram, shouldn't the serial clock line be labelled SCL, not SLC?
Peter G. commented:
It's nice to see columns from highly experienced industry insiders like Mr. Lim, but EDN ought to be more careful to make sure its writers' affiliations are clearly disclosed alongside all the content they provide. Mr. Lim's employment by Tektronix is not mentioned here or on the page linked to under his byline.
