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Scope Guru on Signal Integrity

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Jit Lim, Tektronix senior technologist for high-speed signal analysis, has an EE degree from the Massachusetts Institute of Technology and more than 20 years of experience in the test-and-measurement industry. He has also designed some of Tektronix's highest-performance real-time scopes and published numerous technical papers. Lim brings his extensive experience in signal integrity, jitter measurement, and high-speed-signal physical-layer characterization to these blog posts.

My Yahoo

Selecting the right probe, part 2

Jit Lim
Posted by Jit Lim on February 21, 2012

From guest blogger Gregory Davis: Selecting the right probe is an all-important choice when it comes to acquiring a signal. As we discussed in my last post, not all probes are created equal. Many times you can just use the probes supplied by the test instrumentation manufacturer, but there are times when you may want to consider other options based on the signal you are acquiring. I previously dis ...... Read More

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Selecting the right probe: It’s not just how it feels

Jit Lim
Posted by Jit Lim on February 13, 2012

From guest blogger Gregory Davis: In previous posts we’ve shared a variety of explanations and tips about ways to look at and analyze your signals once a measurement has been made. Now we’re going back, way back—not necessarily to a time where only troglodytes existed, but back to the moment in time when you think about acquiring your signal. It’s the all-important mome ...... Read More

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Which jitter measurement is correct? Part 2

Jit Lim
Posted by Jit Lim on January 19, 2012

Last week I shared a recent discussion around jitter measurement correlation. As a follow-on to that discussion, my colleague Mark Guenther shared some additional insights. Let’s return to the original question of why don’t the Rj/DJ measurements match the TJ(BER=1×10-12) expected result, given the ~14 multiplier for RJ. Jitter estimation based on RJ/DJ separation depends in par ...... Read More

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Which jitter measurement is correct?

Jit Lim
Posted by Jit Lim on January 10, 2012

As you might have read in the last entry of 2011, Jit is sharing the blogger role in 2012 and is giving a number of us what we asked for – the chance to blog about signal integrity challenges. Consider us scope gurus in waiting. My name is Randy White and I get to kick off the new year. I’m the serial applications technical marketing manager at Tektronix. This is such a great role be ...... Read More

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The Scope Guru meets “jolly” old St. Nick

Jit Lim
Posted by Jit Lim on December 21, 2011

As we march toward the end of another year and wind down for the holidays, I’d like to say thank you to all of my readers. For the past two and a half years, I’ve enjoyed sharing my insights and hearing your comments on the signal integrity issues that we encounter as we do our jobs. I hope our interactions have been beneficial and in some way made your jobs a little easier. In the s ...... Read More

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Don’t be like Tiger—Keep your serial buses out of contention

Jit Lim
Posted by Jit Lim on December 16, 2011

After a long and highly public dry spell, Tiger Woods is back in contention with his first tournament win in two years. For Tiger, being in contention is a very good thing.For electrical designers working on high-speed serial buses, however, contention is very bad thing. The outcome is not win-win when your memory modules or A/D converters and I/O devices engage in mortal combat for control of the ...... Read More

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Don’t throw out that passive probe just yet

Jit Lim
Posted by Jit Lim on December 12, 2011

In today’s world of high-speed circuits, the active voltage probe has become the “go to” tool for connecting to signals. Active probes provide wider bandwidths and lower capacitive loading, making them a good choice for measuring high-frequency signals or high-impedance circuits. They are often the probe of choice when measuring frequencies in the lower frequency ranges, as we ...... Read More

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Slicing up the eye

Jit Lim
Posted by Jit Lim on November 29, 2011

Any successful serial communication system design includes a receiver that can make a decision at an instant in time as to whether the transmitted serial stream is above or below a particular threshold voltage. From this it decides whether the incoming signal is a data 1 or a data 0. Sensible system designers place this decision point as far as possible from rising edges, falling edges, high level ...... Read More

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YouTube for Engineers. Really!

Jit Lim
Posted by Jit Lim on November 22, 2011

While enjoying the great American holiday—Thanksgiving—my thoughts go to non-work activities like football or watching videos of someone on YouTube doing crazy stunts. YouTube has become America’s Funniest Home Videos on Google. But now it’s gaining more and more traction as a source for instructional content. When searching on it for “oscilloscope measurements,& ...... Read More

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Signal access, timing analysis drive faster DDR memory-system debug

Jit Lim
Posted by Jit Lim on November 16, 2011

The ramp-up in memory-system speed and capacity over the past few years has been incredible and has opened the door for a greater role for DRAM in computer systems. Capacities in the hundreds of gigabytes are becoming commonplace in high-end servers, and high-speed memories are now being asked to lighten the burden on CPUs for memory-intensive tasks. With this speed increase comes challenges for v ...... Read More

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Why decompose jitter when you can get a true BER?

Jit Lim
Posted by Jit Lim on November 10, 2011

When high-speed serial or optical engineers have access to a BERT (bit-error-rate tester), they can effectively determine design performance by connecting their device under test to the BERT and get a true bit error ratio and a TJ (total jitter) number, or TJ@BER. These results typically are suitable for most compliance test specifications on the market today. So why would you want to break down j ...... Read More

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Are you seeing UI shrinkage?

Jit Lim
Posted by Jit Lim on November 2, 2011

High-speed signals are susceptible to signal-integrity issues because they involve very fast edges and very narrow UIs (unit intervals) or bit times. As the data rate for a PHY communication link increases, two things happen: The UI narrows and the rise time of the signal decreases. For example, when comparing a 5 Gb/s pulse with an 8 Gb/s pulse, the UI width drops dramatically from 200 ps to 125 ...... Read More

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