Revisiting “Universal Memory”

Is it possible for any new memory technology to compete with DRAM and NAND and claim the title of “Universal Memory?”

This question has been debated at numerous conferences. Arguments in support of the issue point to the higher performance, nonvolatile data storage, and smaller die size of several new and emerging memory technologies. Others are skeptical that any new memory technology will ever gain the volume necessary to achieve the cost per bit needed to replace 10-year old and 20-year old established memory technologies.

Adesto’s product announcement highlighted in the previous blog provides evidence of another contributing element in that discussion.

The fundamental argument against any new memory technology competing with DRAM and NAND is that those established technologies already have a defined niche in the existing OEM architectures. The prospects of any new memory technology achieving a cost/performance advantage in the main memory array of a PC or as a laptop solid-state disk drive replacement just doesn’t seem feasible.
 
The issue revolves around identifying a market entry point that will generate enough demand to propel a new technology down the manufacturing learning curve. The issue also requires identifying enough additional applications that can be addressed as the technology gains market momentum and additional infrastructure support. The new technology still has to have the fundamental technical potential to achieve even higher levels of cost/performance over several decades, but it also has to enable some new application or support some new level of performance remarkable enough to inspire higher levels of OEM design creativity.

Finding that kind of market entry point is clearly a challenge when the stated objective is to compete with DRAM or NAND.

However, the concept of a technology enabling a standard manufacturing process that supports both high-performance nonvolatile memory and high-performance logic changes the long-held assumptions of semiconductor production and permanently alters the value ratio between logic designs and memory cells.
 
Now the range of possible market entry points suddenly becomes much wider. Now the concept of “competing with” DRAM and NAND in existing architectures changes to the clear possibility of “replacing” DRAM and NAND by enabling radically new architectures. 
 
When we combine Adesto’s Core Technology Platform with the work of companies currently focused on stand-alone memory designs, we get the first glimpse of the full potential of the new and emerging memory technologies.
 
The “memory” technology race is then no longer about competing with DRAM or NAND on the cost per bit of volatile or nonvolatile memory. The “memory” technology race begins the shift toward altering computing architectures to the extent that current memory product distinctions are no longer critical in future designs.

This is the consolidated vision shared by technology strategists in North America, Europe, and Asia who continue to accelerate the research in the new and emerging memory technologies.