Michael Demler
Mike Demler has more than 30 years of experience in hi-tech industries spanning semiconductors, software, digital media, and wireless technology.
His career began as an IC designer with Texas Instruments, followed by the GE Corporate R&D Labs, Datel, and Micro Networks where he authored the book "High Speed Analog to Digital Conversion." He then moved on to the EDA industry, where he has held business development, strategic and product marketing positions at Synopsys, Nassda, Cadence, and Antrim Design Systems. Mike is also an inventor with eight US patents.
Prior to joining EDN, Mike worked as a Strategic Analyst with DIGDIA, where he focused on the impact of disruptive technologies throughout the wireless industry ecosystem.
Along with an MBA from San Jose State University, he earned his MSEE at Southern Methodist University, and a BSEE degree from the State University of New York at Buffalo.
Email: michael.demler@cancom.com
IC Design CornerLink This | Email This | Comments (0) One EDA/T&M couple is "in a relationship", while another is getting married.Synopsys and Munich-based test and measurement instrument supplier Rohde & Schwarz have announced that they are collaborating on solutions for the design and verification of LTE and LTE-Advanced chipsets to be used in mobile handsets and wireless basestations. Synopsys will be providing a 3GPP (3rd Generation Partnership Project) standard-compliant LTE library for the System Studio and... MoreLink This | Email This | Comments (0) Carbon Design Systems and MIPS Collaborate on Virtual PlatformsCarbon Design Systems and MIPS Technologies have announced that they are collaborating to create and distribute virtual platform models of MIPS processor IP (intellectual property) cores. By creating the processor models from the production RTL (register transfer level) code for each MIPS core, Carbon is promising 100% cycle accuracy. MIPS will integrate the models and virtual platforms with... MoreLink This | Email This | Comments (0) Embedded Systems Conference wrapupI had a summary report of the Silicon Valley Embedded Systems Conference (May 2 nd - 7 th ) nearly ready to publish earlier this week, but due to a WordPress failure my entire post went poof! So apologies for the lag, but I think that ESC had such a wealth of content that it is worth revisiting… even if a bit late. For the EDN Editorial staff, ESC events kicked off in a big way... MoreLink This | Email This | Comments (1) Springsoft's Certitude checks the checker for RTL designsEDA vendor Springsoft has announced enhancements to their Certitude functional qualification system, a set of tools that you can use to check the robustness of the checking mechanisms and stimuli in your functional verification testbenches for IP modules and SoC (system-on-chip) designs. Certitude provides technology that you can use to automate analysis of the effectiveness of your HDL... MoreLink This | Email This | Comments (0) SoC Virtual Conference goes LIVE on Thursday morning, May-12thTomorrow morning I’ll be online early (8:15 Pacific Daylight Savings Time) to kickoff the UBM Electronics/EETimes System on a Chip virtual conference . I think that the website mistakenly has EST times listed, so please be aware that we will actually start at 11:15 Eastern Daylight Savings time. If you haven’t already registered, I encourage you to do so by clicking on... More |
| Next >> |
| Blogs | Recent Posts | Total Posts |
|---|---|---|
| IC Design Corner | 39 | 39 |
