Michael Santarini

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DesignCon 2008: One step forward, two steps….

I attended DesignCon last week and covered two events: “ Where’s the ROI on DFM?” , which was a lively business panel, and a panel moderated by EDA industry analyst Gary Smith on functional verification . I actually planned to write-up a few more events but was sad to find that the others I attended lacked substance and were largely product and/or marketing pitches.... More

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EDAC CEO Forecast: 2% growth for EDA revenue in 2008? EDA blues or blue skies ahead?

Just got back from the EDA Consortium’s annual EDA CEO Forecast and for the most part the CEOs seemed particularly gloomy when it came to revenue forecasts for the year. In brief, the CEO’s didn’t offer any forecasts but Mentor CEO Wally Rhines, whose company is in a quiet period and thus could not give a prediction for EDA industry growth in 2008, pointed to a report from... More

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My IC reliability cover story and my upcoming DesignCon DFM panel

Hi folk, I’ve been in hunkered down mode for the last few weeks researching and writing my next cover story. This one’s on IC reliability. It’s a subject I haven’t tackled before and quite frankly is a subject I haven’t seen too much coverage about, even the EE trade books. I actually learned a quite a bit of information about how design groups and more so... More

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Brave, Brave, Brave Sir Robin…Saxby

EDN’s sister publication Electronics Weekly has a video clip of ARM’s Sir Robin Saxby receiving the Elektra Lifetime Achievement award …way to go Sir Robin! More

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Calypto RTL to ESL equivalence checker gets vote of confidence

A few years ago when EDA startup Calypto introduced its SLEC (sequential logic equivalence checker) tool , I thought it was a very promising technology. One of the biggest issues in ESL modeling is ensuring that the block or design you are modeling at an ES level (in C++, SystemC or ANSI C, etc.) is functionally the same as the RT level implementations. Not having a way to tell if they are... More