Feb 14 2008 4:59PM | Permalink | Email this | Comments (6) |
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I attended DesignCon last week and covered two events: “Where’s the ROI on DFM?”, which was a lively business panel, and a panel moderated by EDA industry analyst Gary Smith on functional verification.

I actually planned to write-up a few more events but was sad to find that the others I attended lacked substance and were largely product and/or marketing pitches. I’ve been attending DesignCon my whole career from the days when it was called Design SuperCon and was run by HP. I’ve moderated several panels over the years and even hosted technical tracks. A few years ago, the IEC took over the conference and actually improved it. I think the shows back in 2006 and 2007 were both great with some strong keynotes and panels as well as t...Read More

Feb 7 2008 11:18PM | Permalink | Email this | Comments (6) |
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Just got back from the EDA Consortium’s annual EDA CEO Forecast and for the most part the CEOs seemed particularly gloomy when it came to revenue forecasts for the year. In brief, the CEO’s didn’t offer any forecasts but Mentor CEO Wally Rhines, whose company is in a quiet period and thus could not give a prediction for EDA industry growth in 2008, pointed to a report from one of the financial firms that showed a historic correlation between semiconductor R&D expenditures and EDA revenue for the last several years. If the correlation holds true to form, the analyst report extrapolates that the EDA industry will only grow 2% in 2008. None of the CEOs on the panel disputed that number.

It is worth noting that Synopsys’ CEO Aart de Geus could not offer a prediction because like Rhines his company is in a quiet period and has yet to report its qu...Read More

Jan 30 2008 6:18PM | Permalink | Email this | Comments (2) |
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Hi folk, I’ve been in hunkered down mode for the last few weeks researching and writing my next cover story. This one’s on IC reliability. It’s a subject I haven’t tackled before and quite frankly is a subject I haven’t seen too much coverage about, even the EE trade books.

I actually learned a quite a bit of information about how design groups and more so semiconductor companies and IC manufactures look at reliability throughout product development. It’s actually a story that could have been a small novella. In print, space is always a bit limited so the print version of the story will cover the more traditional failure mechanisms designers and manufacturers need to watch out for. Some of those failure mechanisms pop up one process generation then are handled quickly by the semi guys. Some failure mechanisms are starting to rear their...Read More

Jan 22 2008 1:41PM | Permalink | Email this | Comments (0) |
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EDN’s sister publication Electronics Weekly has a video clip of ARM’s Sir Robin Saxby receiving the Elektra Lifetime Achievement award…way to go Sir Robin!

Jan 15 2008 2:04PM | Permalink | Email this | Comments (0) |
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A few years ago when EDA startup Calypto introduced its SLEC (sequential logic equivalence checker) tool, I thought it was a very promising technology. One of the biggest issues in ESL modeling is ensuring that the block or design you are modeling at an ES level (in C++, SystemC or ANSI C, etc.) is functionally the same as the RT level implementations. Not having a way to tell if they are the same is a bit of a roadblock. Also, for ESL synthesis to reach its full potential, designers would need a way to ensure the ESL output of a given synthesis tool was functionally the same as the RTL version and vice versa.

When Calypto introduced SLEC a few years ago, it showed great promise in solving those problems. The tool claimed to check that models and synthesis output at different levels were essentially the same. The to...Read More