Mar 18 2010 1:19PM | Permalink | Email this | Comments (0) |
Blog This! using:  Blogger.com | LiveJournal |

One of the wonderful things about this job is the chance to sit in on papers unrelated to my beat. The subject of this posting, a paper at EDN's Designing with LEDs seminar, is a case in point. By just sitting there for 45 minutes I heard some hard-earned lessons from a different world, but with important implications in the SoC space.

The presenter was Geof Potter, a power technologist at Texas Instruments and long-time hand in power-supply design. After a quick review of what goes into an LED lighting assembly—basically, a power supply and a bunch of LEDs—Potter started to decompose the assembly—called a luminaire, by the way—into its components and to discuss the impact of each on lifetime and reliability.

The two terms are different in Potter's world, by the way. Lifetime refers to the length of s...Read More

Mar 17 2010 8:17AM | Permalink | Email this | Comments (2) |
Blog This! using:  Blogger.com | LiveJournal |

DRAM giant Hynix and IP vendor Innovative Silicon today announced work that offers an alternative future for the DRAM industry beyond the 30nm half-pitch. Using 3D transistors similar to FinFETs, the two companies have demonstrated behavior similar to the floating-body effect in SoI planar transistors. IS claims the effect is strong enough and has the right characteristics to implement a capacitorless, one-transistor DRAM that can meet DDR3 voltage, power, and performance specs at and beyond the 50nm half-pitch. By 30nm, according to IS senior vice president of marketing and business development Jeff Lewis, the floating-body memory will have a significant cost advantage over conventional stacked-capacitor DRAM as well.

...Read More

Mar 10 2010 5:55PM | Permalink | Email this | Comments (6) |
Blog This! using:  Blogger.com | LiveJournal |

Static timing analysis (STA) was nearly an instant success at timing closure 15 years ago. But except for creating partitioning/scheduling algorithms to parallelize the algorithms for multicore CPUs, nothing much has changed since, if you will grant that statistical timing analysis is a separate subject.

This languishing has allowed the number of instances in a design, the number of modes in which a design must be analyzed, and the number of process corners each to grow enormously, while the speed of STA remained tied to the comparatively much slower growth in computing power. Consequently, run-times for full designs across modes and corners have become enormous—days, in some cases. That has turned STA from an elegant, fast tool into a powerful, trusted, but ponderous necessity, consuming licenses and days of precious schedule with abandon. If there were a way to spe...Read More

Mar 10 2010 9:42AM | Permalink | Email this | Comments (2) |
Blog This! using:  Blogger.com | LiveJournal |

TierLogic, yet another large and expensive FPGA start-up that has been in stealth mode for years, today unveiled a radical approach to increasing the density and utility of large programmable logic devices. Like previously-announced Tabula, TierLogic describes their design as a 3D FPGA. But the two approaches are totally unlike each other, and neither is related to the concept of 3D ICs—involving stacked dice and through-silicon vias—that is currently the hot topic in SoC-of-the-future circles.

TierLogic's big idea is elegant and audacious: increase the density of FPGAs by moving all the configuration memory—not the data memory or the look-up-table (LUT) memory, but the RAM cells that control the interconnect muxes—out of the silicon. Removing...Read More

Mar 8 2010 12:55PM | Permalink | Email this | Comments (0) |
Blog This! using:  Blogger.com | LiveJournal |

As the AMS content of SoCs has increased, the need for tools to deal with analog functions in an SoC design flow has increased as well. Nothing will replace SPICE as a transistor-level modeling language. But just as with digital circuits, there is a need for higher levels of abstraction for the analog blocks of SoCs. Language extensions for RTL languages VHDL and Verilog have met part of the need, but there is still a gap at the higher levels in the flow: between the primarily algebraic representations of transfer functions in MatLab and the more implementation-directed models of Verilog-AMS. OSCI has a working group focused on this issue, and today the group released Version 1.0 of its AMS standard.

The working group had previously released a reference manual and while paper on their work. But with the official release of the 1.0 st...Read More