Nov 18 2009 3:58PM | Permalink | Email this | Comments (0) |
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As the pressure of growing data traffic bears down on cellular networks, service providers are turning to femtocells as an achievable near-term solution. This growing interest is speeding the maturation of the femtocell market and triggering a scramble among silicon providers.

The proximate issue is network capacity, a crisis triggered by the huge data bandwidth appetites of smartphones. Not only are these handsets rich in Web-gnawing applications, but, as Interdigital fellow Bob DiFazio observes, "the new mobile Internet traffic is not optimized for limited bandwidth. HTML is a hundreds of times greater load than bandwidth-conserving formats like Widsets or Bluepulse."

But the options for increasing air bandwidth are few, and scattered along an uncertain timeline. The obvious step—upgrading the network t...Read More

Nov 16 2009 9:07AM | Permalink | Email this | Comments (0) |
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An announcement today by three companies—semiconductor vendor Fulcrum Microsystems, 10G Ethernet switch vendor Arista Networks, and network test vendor Ixia—serves to illustrate the ferment bubbling away inside the very concrete-and-steel data centers that are the reality behind the cloud computing nebulosity. The three vendors teamed up to make some performance measurements on an emulated 10Gbit Ethernet data-center backbone.

The driving force behind the work, according to Fulcrum director of product marketing Gary Lee, is an architectural shift in the networks within the giant data centers. Given the scale of deployment forecast for coming years, system operators can't afford to wire together individual servers, or even racks ...Read More

Nov 9 2009 12:15PM | Permalink | Email this | Comments (3) |
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As SoCs become more complex, the concept of using a network to replace the bus or crossbar switch as the interconnect backbone on the chip has become more popular. From thesis material a few years ago, the NoC is now actually shipping, carefully buried in some consumer products.

The underlying concept of a NoC, such as those from Arteris, Silistix, or Sonics, is simple enough. It begins with the idea that all traffic between the major functional blocks in an SoC should be packetized. Packetization, in turn, allows great freedom to optimize the physical interconnect between the blocks. Ordinarily, for example, a backbone bus or central crossbar switch must be as wide as the width of the widest port on any of the IP blocks it serves. But if the traffic is pac...Read More

Nov 3 2009 1:23PM | Permalink | Email this | Comments (0) |
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In a plenary talk at the International Test Conference this morning Intel fellow Shekhar Borkar offered a tightly-reasoned description of how IC architectures will look in a few years, with some observations about the future these architectures imply for test engineers. The talk certainly represented the views of Intel's director of microprocessor technology, and may indicate the general direction of thinking within the company.

Starting with the familiar, Borkar discussed just what kind of chip one could build today, and tomorrow, with a power budget of 65W. Today, he said, you could combine about 50M logic gates with about 6 MB of cache: a typical dual-core high-end CPU chip. But ten years from now, Borkar warned, scaling in both energy-efficiency and delay will have slowed down considerably, while the magnitude of process vari...Read More

Nov 2 2009 8:04PM | Permalink | Email this | Comments (0) |
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An evening panel session at the International Test Conference this evening reviewed decades of the research work at Stanford University's Center for Reliable Computing, and nearly turned into an encomium for one man: the Center's director, Ed McCluskey. By offering statements from many CRC members past and present, the panel showed the remarkable range of technology vital to the industry in which CRC—and McCluskey—have played a seminal role.

In the early days, according to the first panelists--including Dan Siewiorek, who spoke by pre-recorded video--the center stayed close to the implications of its name, doing original work on such topics as fault-tolerant computing circuits, triple module redundancy, ...Read More