Jun 29 2009 6:34PM | Permalink | Email this | Comments (0) |
Blog This! using:  Blogger.com | LiveJournal |

Following an active panel on DDR3 DRAM, last week's Denali Memcon offered up a second panel topic: low-power memory design. That's a wide enough topic to allow for a range of discussions, and the panelists--Mostafa Abdulla of Numonyx, Roger Isaac of Silicon Image, Areski Maklouf from ST-Ericsson, and Howard Sussman of Etron—ranged all over it.

In opening statements, Maklouf said that LPDDR is a major issue for the platform architect. "Architects must work with memory providers to find a good solution," he said. Moving in a different direction, Isaac pointed out that no matter how cleverly you architected it, LPDDR was not going to make it for much longer. "We can get 3.2 GB/s per chip out of LPDDR2," he said, "but for the next generation of handsets, w...Read More

Jun 29 2009 7:50AM | Permalink | Email this | Comments (0) |
Blog This! using:  Blogger.com | LiveJournal |

One sure indication that low-power FPGAs are beginning to penetrate the domain of small ASICs in power-constrained applications is that the FPGA vendors are running headlong into new design requirements. That proof is reflected in the announcement this morning of a new Cyclone III line—the Cyclone III LS—from Altera. The mid-sized FPGA features low power consumption, plus two feature sets rather novel for Altera: design-protection to prevent reverse-engineering from discovering the programming data, and hardware-level isolation within the logic array to allow for both data security and hardware redundancy.

The low-power credentials of the part are notable for an SRAM-based device. Altera manager of product marketing Umar Mughal said the chip dissipated less than a quarter Watt of static power, primarily through use of TSMC's 60L low-leakage process. That proc...Read More

Jun 29 2009 7:43AM | Permalink | Email this | Comments (0) |
Blog This! using:  Blogger.com | LiveJournal |

Many—maybe even most—SoC design teams use C or C++ to explore algorithms and the behavior of their system before they begin implementation. That makes it entirely natural for designers of new blocks—as opposed to those who are importing previously-used IP at RT level—to wish there were a way of synthesizing the C code directly into RTL to insert it into their implementation flow. After all, much of this behavioral C will get incorporated into testbenches for the verification team, so why not capture the design behavior as well?

In fact for some types of blocks, many teams already to this today. A number of tools will synthesize signal-processing datapaths from a carefully-written C description of the algorithm into a very serviceable RTL description of the necessary hardware. In some applications, such as wireless baseband signal processing, these...Read More

Jun 25 2009 7:50AM | Permalink | Email this | Comments (0) |
Blog This! using:  Blogger.com | LiveJournal |

LSI officially launched a new era in disk read-channel technology this week with the RC9500: a new generation mixed-signal read channel intellectual property (IP) core cluster. The block, intended for integration with a drive vendor's IP to create a single-chip drive electronics subsystem, plants two milestones at once. The IP is LSI's—and possibly the industry's—first adventure into 40 nm. And it appears also to be the first application of a low-density parity-check (LDPC) algorithm in read channel products. LSI intends the IP for the coming generation of 500 GB/disk 2.5-inch, and 1 TB/disk 3.5-inch drives.

The 40 nm part is pretty self-explanatory. LSI director of product marketing Gordon Paulus said that the technology allows the read channel to reach 4 Gb/s within the power budget customers hav...Read More

Jun 24 2009 10:39AM | Permalink | Email this | Comments (0) |
Blog This! using:  Blogger.com | LiveJournal |

Solido Design has, as previously projected, added another tool to their Variation Designer platform. Well-Proximity is the first tool in a second package that runs on the Variation Designer Platform, complementing the Statistics package.

The well-proximity issue, according to Solido corporate applications engineering manager Kristopher Breen, becomes an important source of process variations at 90 nm. But to date, most design teams have either been ignoring the effect—risking significant yield loss or outright design failures in their analog and custom circuits—or they have been inserting guard-band spacing around the edges of well implants, trading die area for safety.

The mechanism th...Read More