Nov 23 2009 9:06PM | Permalink | Email this | Comments (4) |
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The argument between ASICs, ASSPs, and FPGAs has ranged over the same territory for a decade. FPGAs are slower, more power-hungry, and more expensive than comparable ASICs. But FPGAs require no NRE, require little physical design or verification, and provide prototypes in hours or days instead of weeks. In outline, the terms of the debate haven't changed: FPGAs make sense for low- to moderate-volume designs of low to moderate complexity, in which neither power nor performance is critical and there is no close fit in the ASSP world.

But this apparent stasis conceals a lot of activity at the margin, where the technologies have significant overlap. In part this activity is a gobbling of market share by FPGAs as a result of the global economic catastrophe. With end-user demand all but gone and returning only furtively, "moderate volume" includes a lot more designs t...Read More

Nov 20 2009 9:53PM | Permalink | Email this | Comments (0) |
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Some time ago, as the storm of recession broke over the industry, we encouraged companies to look quickly to developing markets for demand that was not based on conspicuous consumption. Since then there has been a devastating collapse in end-user demand across the industrialized nations. In contrast, countries such as China and India appear to be using their banks to support their citizenry—rather than committing ordinary citizens to enrich the banks. Our dim view of developed-world demand seems to have been justified.

Apparently European companies—always of necessity more outward-looking than their US competitors—are starting to believe similarly. According to a report in today's Financial Times, companies including Philips, carmaker Renault, and German truck-builder MAN are planning to get over half their sales from emerging markets by 2015. Electrica...Read More

Nov 18 2009 3:58PM | Permalink | Email this | Comments (0) |
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As the pressure of growing data traffic bears down on cellular networks, service providers are turning to femtocells as an achievable near-term solution. This growing interest is speeding the maturation of the femtocell market and triggering a scramble among silicon providers.

The proximate issue is network capacity, a crisis triggered by the huge data bandwidth appetites of smartphones. Not only are these handsets rich in Web-gnawing applications, but, as Interdigital fellow Bob DiFazio observes, "the new mobile Internet traffic is not optimized for limited bandwidth. HTML is a hundreds of times greater load than bandwidth-conserving formats like Widsets or Bluepulse."

But the options for increasing air bandwidth are few, and scattered along an uncertain timeline. The obvious step—upgrading the network t...Read More

Nov 16 2009 9:07AM | Permalink | Email this | Comments (0) |
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An announcement today by three companies—semiconductor vendor Fulcrum Microsystems, 10G Ethernet switch vendor Arista Networks, and network test vendor Ixia—serves to illustrate the ferment bubbling away inside the very concrete-and-steel data centers that are the reality behind the cloud computing nebulosity. The three vendors teamed up to make some performance measurements on an emulated 10Gbit Ethernet data-center backbone.

The driving force behind the work, according to Fulcrum director of product marketing Gary Lee, is an architectural shift in the networks within the giant data centers. Given the scale of deployment forecast for coming years, system operators can't afford to wire together individual servers, or even racks ...Read More

Nov 9 2009 12:15PM | Permalink | Email this | Comments (3) |
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As SoCs become more complex, the concept of using a network to replace the bus or crossbar switch as the interconnect backbone on the chip has become more popular. From thesis material a few years ago, the NoC is now actually shipping, carefully buried in some consumer products.

The underlying concept of a NoC, such as those from Arteris, Silistix, or Sonics, is simple enough. It begins with the idea that all traffic between the major functional blocks in an SoC should be packetized. Packetization, in turn, allows great freedom to optimize the physical interconnect between the blocks. Ordinarily, for example, a backbone bus or central crossbar switch must be as wide as the width of the widest port on any of the IP blocks it serves. But if the traffic is pac...Read More