Steve Leibson spent eleven years with EDN, working as a regional editor, Executive Editor, and Editor in Chief. Before joining EDN and, later, The Microprocessor Report, he designed computer systems and related products at Hewlett-Packard and EDA pioneer Cadnetix. Currently, he's Tensilica's Technology Evangelist, and Elsevier recently published his third book, Designing SOCs with Configured Cores. His HP history Web site on early HP desktop calculators and computers is at www.hp9825.com.
Sep 2 2008 6:10PM | Permalink | Email this | Comments (6) |
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This article about the Large Hadron Collider (LHC) just appeared on the MSNBC Web site. The article, written by Alan Boyle, discusses court cases brought against the startup of the LHC because there’s a small-but-finite possibility that it could create a microscopic black hole that will then proceed to eat the planet. Physics theorists have said enough so that I conclude we just don’t know one way or another even though safety reports deny the possibility of creating a black hole. The energies are too low, apparently. The report states that common cosmic-ray collisions are many times more energetic than the collisions created by the LHC. We do not see lots of mini black holes created by these cosmic-ray collisions, so it’s unlikely that the LHC can create a black hole.
I&rsqu...Read More
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Aug 30 2008 5:22PM | Permalink | Email this | Comments (0) |
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After a year of near inactivity, I got the chance to update my history site, www.HP9825.com, with information about and stories of the development of interface cards for the Hewlett-Packard 9825A desktop computer, manufactured in the late 1970s and early 1980s. I finally got the time to transcribe a video interview that I recorded late last year and was recently able to contact three more people that I’ve not spoken to for 30 years! All had valuable information, stories to add, and puzzle pieces I didn’t have in my puzzle box. You will find the new information here:
http://www.hp9825.com/html/interfaces.html
It was important for me to get back to work on this site. The principals are all in their 50s or older and they are starting to pass on. We lost another on...Read More
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Aug 26 2008 11:16AM | Permalink | Email this | Comments (0) |
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Alex Mericas’ Hot Chips presentation delivered some insights into low-power processor design that IBM has gleaned from designing it’s series of server-class microprocessors: Power4, Power5, and Power6. These insights aren’t new. People involved in processor design know these tricks. But perhaps they’re more solid with IBM’s weight behind them.
Here are the basic concepts Mericas espoused:
Related entries in: ASICs | Processors | SOC (System on a chip) |
Aug 26 2008 10:57AM | Permalink | Email this | Comments (2) |
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Sam Williams, a PhD student working under UC Berkeley’s Professor and Processor Guru Dave Patterson, gave a polished Hot Chips talk on a metric that allows undergrads (and, in my mind, overly busy design engineers) to determine when they’ve sufficiently optimized software to run on multicore parallel processors. Note that this model is about optimization, not writing correct parallel programs. "If you can't write a correct parallel program," said Williams, "you shouldn't be worried about optimizing it."
William's concept is called the “Roofline Model” and I thought about summarizing it here, but I’d need a blog entry the length of the presentation to do it. So go get a copy yourself on Williams’ Web page.
Essentially, the Roofline model tries to pair inform...Read More
Aug 26 2008 10:31AM | Permalink | Email this | Comments (5) |
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Here’s a crazy idea: extend memory coherency for an SMP system across a LAN. Now why in the world would you do something so crazy? Well, it turns out that servers have a lot of trouble distributing loads and allocating resources. The result is low server utilization. SMP systems partially solve this problem by creating a pool of processors linked by coherent memory. Any processor can restart any stalled task because of the coherent memory. However, the number of processors in a cluster is limited and processors in other SMP clusters located in other parts of a server farm at the other end of LAN piping do not have a coherent-memory link so they cannot be easily used for load distribution without a lot of data movement across the LAN. That’s super slow.
So, the answer is simple. Just extend memory coherency across the LAN. That’s the solution that ...Read More
Related entries in: Computers, boards, buses | Microprocessors |
| Blogs | Recent Posts | Total Posts |
|---|---|---|
| Leibson's Law | 1 | 291 |