Jun 2 2009 5:42PM | Permalink | Email this | Comments (0) |
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The Electronic Component Technology Conference (ECTC) , is sponsored by the IEEE’s Component, Packaging and Manufacturing Technology Society (CPMT) and the EIA (Electronic Industry Association). For the Component and Packaging community this is the pre-eminent conference on such topics during the year. Their 59th annual meeting was held last week in San Diego. Despite the economy and H1N1 “pandemic” 520 paid attendees ( down ~ 25 % from last year) gave 262 oral and 74 poster presentations in 36 technical sessions. Unfortunately many of the speakers from Asia...Read More

May 24 2009 1:30PM | Permalink | Email this | Comments (0) |
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As we have discussed many times before, one of the important aspects of 3-D technology process flow is how you handle wafer thinning. A typical process flow for temporary bonding involves the carrier wafer and/or the device wafer being coated with an adhesive, bonding of the device and handle wafers, processing of the wafers and then removal of the carrier, hopefully without ever having to handle the thinned wafer.

In all options there are two main components: (1) the materials used as temporary adhesive; and (2) the automated equipment used to bond and debond the wafer. Material suppliers have all been trying to increase the thermal stability of their materials to allow for higher temperatures during the thinning and backside proce...Read More

May 17 2009 9:34AM | Permalink | Email this | Comments (0) |
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Philips spun out its semiconductor division and a lot of its debt as NXP in the fall of 2006. Ever since then, parts of the company have been sold off to lighten this debt load. Shortly after NXP announced the joint venture of its wireless division with STMicroelectronics, and the subsequent sale of this venture to ST-Ericsson, last summer, its 150 mm wafer plant in Caen, France, was put up for sale.

This NXP site has a history in 3-D passive integration, having successfully launched RF-SiP modules based on its so-called PICS passive integration technology in 2004. Several hundred million modules have reportedly been sold since then. Despite this success, NXP announced its plans to sell this site in 4Q08. For our previous discussion ...Read More

May 9 2009 6:34AM | Permalink | Email this | Comments (0) |
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Design, Automation and Test in Europe (DATE) was held this year in Nice, France, which is certainly a NICE place for a DATE. I think that’s two double entendres in one sentence, certainly a record for me.

As part of this year's conference, Erik Jan Marinissen, IMEC; Yann Guillou, ST-Ericsson; and Geert Van der Plas, IMEC held a session entitled "3D Integration – Technology, Architecture, Design, Automation and Test." Certainly apropos for this blog, nes pas?

During his keynote address on “The Promise of TSV,&...Read More

Apr 30 2009 11:33AM | Permalink | Email this | Comments (0) |
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Many of you will have already seen the press release that Dresden will be the site of a Fraunhofer 3-D silicon research institute. I decided to dig a little deeper, so I contacted colleagues in Berlin and Munich to learn more.

The newest Fraunhofer center, All Silicon System Integration Dresden (ASSID), will report into old friend Herbert Reichl, head of Fraunhofer IZM, which has branches in Berlin and Munich. The focus of the new center will be on prior-to-BEOL (vias middle) TSV, silicon interposers, thin die integration and 3-D stack formation. The center's goals include:

• TSV in passive and active semiconductor wafers.
• Silicon interposer technologies for high-density wiring and the integration