Mar 19 2010 10:25AM | Permalink | Email this | Comments (3) |
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Editorial colleague Ed Sperling may seem a bit serious in person, but he usually has a pretty upbeat way of observing the electronics industry from a high-level vantage point that alleviates panic. Mind you, I’m not talking about the “happy news” blinders that characterized the PR community in periods like the 1999-2000 pre-crash, but an ability to examine the landscape from 30,000 feet and say, “It’s neither as dire nor as dazzling as it seems, but it’ll be OK.”

Sperling’s work with System-Level Design tests that capability to its limits, since he has to report on the EDA community – a market sector that many in the trade press have declared to be all but dead on arrival. Now of course, a decent business remains for Cadence, Mentor, and Synopsys, and speci...Read More

Mar 16 2010 8:16AM | Permalink | Email this | Comments (1) |
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FPGAs have made their presence felt for years at the Optical Fibers in Communications/National Fiber Optics Engineers Conference (OFC/NFOEC), so it would be easy to breeze past the latest Xilinx preview of a demo at next week’s OFC as just so much puffery. But look again. As FPGAs move directly into multiplexer/transponder duties (what Xilinx calls a ‘muxponder’), the importance of reconfigurability for handling the bitstream becomes paramount.

If you’ve been paying attention to the 802.3ba high-speed group within IEEE, you know that Ethernet is following a two...Read More

Mar 12 2010 10:08AM | Permalink | Email this | Comments (4) |
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We’ve been watching the board-level embedded folks like Mercury Computer Systems and Pentek shift over the last couple years from DSPs to high-end FPGAs for real-time filtering and signal processing. Now, Altera’s senior DSP marketing manager Michael Parker has written a piece for EETimes Asia on using the company’s Quartus II, SOPC Builder, and DSP Builder tools for effective implementation of blocks such as FIR filter on a Stratix FPGA.

So far, so good. When Parker concludes that using FPGAs for DSP co-processing is always more efficient than equivalent DSPs, however, I’m wondering if he’s taking into a...Read More

Mar 10 2010 9:13AM | Permalink | Email this | Comments (1) |
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Tier Logic has gotten the occasional mention in this blog as a startup specializing in 3D interconnect, but after the splash made by players such as Tabula, NuPGA, and Abound, one could almost be tempted to ask what the company would do for an encore. But on the eve of Tier Logic’s official “architectural announcement” of March 10, Tier’s vice president of sales and marketing Paul Hollingworth clued me in on the company’s threefold path to profitability, which frankly makes a lot more tactical sense than what I’ve heard from other startups of late.

The company relies on relatively traditional configuration logic in a nine-layer-metal base, but adds TFT...Read More

Mar 8 2010 9:23AM | Permalink | Email this | Comments (0) |
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Ever since the IEEE 802.3 Ethernet high-speed study group approved dual project authorization requests at 40 and 100 Gbits/sec that became 802.3ba, most of the debate regarding next-generation Ethernet has centered on issues such as the channel multiplexing for transceiver modules – will it be x4, x10, x12, and when will a copper alternative in a high channel-count module be preserved? Such debates do have implications for FPGA serdes blocks, to be sure, but they may not seem central to development of future Ethernet MACs.

But there’s also the effort by tight coalitions to develop higher-layer protocols. Two of the longer-history efforts are the Interlaken Alliance ...Read More