News
Accellera approves analog, mixed-signal standard 8/20/2008
To allow the development of standard and tightly integrated Verilog-AMS modules and allow EDA software tool developers to implement EDA tools without ambiguities in the language interpretation, EDA standards organization Accellera announced today that it has approved a new version of its Verilog-analog mixed-signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analog and mixed-signal design and simulation.Altera, Mentor team up to support avionics, military apps 8/19/2008
In support of the growing number of avionics and military applications requiring DO-254-certifiable components, San Jose-based programmable logic device company Altera Corp and Wilsonville, Ore-based IC design tool supplier Mentor Graphics Corp reported today that they are doing joint work to develop tools and methodologies for use in creating DO-254-certifiable IP that targets Altera’s FPGA and HardCopy ASICs.Structured-ASIC option reaches 45-nm node 8/4/2008
Structured-ASIC pioneer eASIC announced today a family of fast-turn ASIC products at 45 nm, combining the zero-NRE (non-recurring expenses) and six-week turnaround of their via-programmed architecture with the performance, density, and power characteristics of the industry's most advanced production node.Intel details PC graphics-aimed 'Larrabee' 8/4/2008
Santa Clara, Calif-based chip giant Intel Corp will present a paper at the Siggraph 2008 conference being held next week in Los Angeles that details features and capabilities for its forthcoming multi-core “Larrabee” architecture which includes a new approach to the software rendering 3-D pipeline, a many-core programming model and performance analysis for several applications.Intel marches once again into microcontroller market 7/23/2008
Combining a single processor-core complex, North- and South-bridge functions, application-specific peripheral blocks, and in some cases an application accelerator, the chips in the family will create an x86-instruction-set alternative to the rainbow of ARM- and MIPS-based SOCs, at least for systems that can tolerate the considerable power and memory footprint involved.In-Depth
Electronic-system-level design: Is there fire beneath the smoke? 8/21/2008
After years of overclaiming and underperforming, ESL design has a role in many design flows. But has anyone noticed?On-chip test capabilities solve the analog-test problem for high-speed serial interfaces 8/21/2008
Including analog-test hardware in an SOC provides visibility into the performance of on-chip serial links, helping to ensure signal integrity and reduce the cost of manufacturing test.Virtualization and multicore x86 CPUs 8/6/2008
The aggressive multicore roadmaps of the x86 chip vendors point to virtualization becoming ubiquitous in the near future. I/O support is the last remaining performance bottleneck for heavily virtualized data-center systems. Fortunately, a number of proven techniques under active development and standardization hope to keep stride with the increasing number of available CPU cores.HDL-design challenges and philosophies for real-world ASIC implementations 7/24/2008
Prototyping with FPGAs works best if you do it with the final ASIC in mind.RF: Will it ever be plug-in IP? 6/12/2008
As SOCs for mobile devices integrate radio circuits, they will need to reuse RF IP. But will they be able to?Experts
IP selection and power supplies 8/21/2008
The failure to fully embrace just one of the two competing power-analysis standards has caused confusion and uncertainty among IP users about power-strategy compatibility.ESL: The state of the industry and what’s next? 8/19/2008
GUEST OPINION: While ESL continues to remain in its infancy, there are signs in the industry that point towards eventual mainstream usage, however the scope of what is needed has to be more inclusive of the entire system-level design and verification flow.Where is EDA going now? 7/10/2008
Some important changes have been altering the EDA landscape for years, and these changes—in the geographic composition of the chip-design community and in the nature of the chip-design process—are now impossible to conceal.Your chip in half the time? 7/9/2008
GUEST OPINION: A project's commercial success depends on designers' ability to deliver silicon on time. That's why the industry recognizes the growing importance of time to results.Third-party-IP providers: Physical-design questions, part two 6/26/2008
Engineers often overlook one physical-design issue for qualifying IP (intellectual-property) blocks: handling routing blockages and overlayer-routing conditions.DesignIdeas
