News
Mentor assembles a test-yield fusion platform 11/2/2009
A pair of new yield-analysis tools kicks off a new fused test and yield product line.Intel, Numonyx to describe stackable phase-change memory array 10/28/2009
Eliminating a diode from the cell, researchers develop a memory that lives entirely in the interconnect stack.Fujitsu launches USB 3.0-to-SATA-bridge chip 10/8/2009
Fujitsu Microelectronics recently announced a 3.0-to-SATA (serial-advanced-technology-attachment)-bridge chip. The company intends the device to act as a connection between a USB (Universal Serial Bus) 3.0 cable and a SATA external-storage device.Mentor unveils strategy at DAC 9/17/2009
Mentor Graphics announced its acquisition of Embedded Alley Solutions as a key component of its Android and embedded-Linux strategy last month at the Design Automation Conference in San Francisco.Tanner EDA announces router, layout-device generator 9/3/2009
At the Design Automation Conference, which took place in July in San Francisco, Tanner EDA introduced the SDL (schematic-driven-layout) interactive autorouter and the DevGen layout-device generator. The company also announced that it is shipping Version 14.10 of its Tanner Tools Pro and HiPer Silicon products, which serve full-custom analog and MEMS (microelectromechanical-system) design.In-Depth
Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces 10/15/2009
A new, all-digital approach to implementing high-speed PHY logic and a DLL offers a path to addressing increasingly stringent market requirements.IP quality lies beyond compliance testing 10/8/2009
Of course you want your standard-interface IP to pass compliance testing. But that accomplishment is just the beginning. Complete quality assurance for IP cores has far more challenges.FPGA architectural power-saving techniques at 40 nm 9/23/2009
As geometries shrink, FPGAs must begin to employ design-specific power-management techniques in order to save power while meeting timing.Outsourcing an IC design: Some advice from the trenches 9/3/2009
In this climate, outsourcing is becoming a mandatory skill for IC-design managers. But it's not intuitively obvious.Addressing interleaved multichannel memory challenges 8/20/2009
Interleaving addresses in multiple DRAM channels can greatly improve memory bandwidth, but it is not a trivial task.Experts
Openness and cooperation create healthy EDA ecosystem 9/29/2009
GUEST OPINION: Competition brings progress, but it helps the customer only if we respect standards and the need for interoperability.Reference-tool flows and process-design kits, part one 9/17/2009
Reference-tool flows and process-design kits have been the basis of chip design since the start of the semiconductor industry. Although these files provide adequate information, they alone do not represent all of the issues.SOI Industry Consortium stalks the “green thing” 8/20/2009
In some cases, the semiconductor's appeal to greeness makes sense, even without adding chlorophyll to the package epoxy.Automation and the smiley face of death 7/9/2009
The pervasive trends of manpower reduction and the shift toward the use of foundry services have created a new set of challenges for designers attempting to bring a prototype design to reality.Closing the ESL gap 6/16/2009
GUEST OPINION: Plenty of commentary has been written about the promise of ESL and how it remains unfulfilled. The truth is that engineers have been successfully designing with ESL tools for years.DesignIdeas
