Design Center

IC Design

Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, and the design methodologies other IC designers are using to become successful.
Top Story
Top Story

Little-known flash-memory features protect data and IP 6/25/2009

Features from block locking to encrypted-password-access mechanisms can prevent unintentional disruption, malicious damage, or copying.

News

Accellera, Spirit Consortium merger hints at future of ESL design 6/11/2009

The merger aims to bridge the language-based design and IP-assembly worlds and will exploit the fact that the two organizations have been working in complementary areas of front-end design and verification.

Akya reveals dynamically reconfigurable logic technology 5/28/2009

IP-based offering reduces risk and increases flexibility of custom chip designs.

EUV prints critical layers for 22-nm SRAM 5/14/2009

IMEC (Interuniversity Microelectronics Center) reports having used ASML’s EUV (extreme-ultraviolet) Alpha lithography tool to print the contact and metal patterns for a 22-nm-node SRAM cell—apparently, the first application of the tool for multiple layers at this density. The SRAM cell is both tiny—at 0.

Power-supply modulation steps up handset-power-amp efficiency 4/9/2009

RF-engineering company Nujira has extended the reach of its efficiency-boosting technology for power amplifiers into the handset. The company has until now focused on the infrastructure side of communications, selling its HAT (high-accuracy-tracking) power-line modulators into applications such as base stations.

IMEC shows flexible packaged-IC assemblies 4/9/2009

Researchers at IMEC (Interuniversity Microelectronics Consortium) and at Ghent University recently demonstrated results from a 3-D integration process using highly thinned ICs with flexible packaging, materials to create fully flexible circuit assemblies. Researchers thinned an IC die to a thickness of 25 microns.
In-Depth

Designing portability into silicon IP 6/11/2009

Design foundry portability into IP cores, rather than applying it after the fact.

Troubleshooting a transaction-level model 6/11/2009

Seemingly minor violations of the TLM 2.0 standard can turn a system-level model into an agent of evil in your design flow.

Eliminate Sallen-Key stopband leakage with a voltage follower 5/14/2009

Novel design techniques help reduce stopband leakage in your filter designs.

RFIDs power themselves 5/4/2009

The IC Insider takes a look at the charge pump of Alien Technology's Alien Higgs RFID.

Power fortunes: Estimating power in FPGA designs 4/23/2009

As FPGAs enter new applications, designers must estimate power consumption early, closely watch it, and then attempt to measure the results.
Experts

Closing the ESL gap 6/16/2009

GUEST OPINION: Plenty of commentary has been written about the promise of ESL and how it remains unfulfilled. The truth is that engineers have been successfully designing with ESL tools for years.

A modest proposal for IP 6/11/2009

The US patent system needs fixing to the point that there are debates over just whose interests we should fix first.

Selecting the correct process geometry and options 5/14/2009

Most of the custom chips today, including ASICs, ASSPs (application-specific standard products), and special-purpose custom chips, have function blocks that do not require leading-edge processes.

"In-design" physical verification is "on-time" physical verification 5/11/2009

GUEST OPINION It's no longer practical to wait until the end of the physical design of an IC to do physical verification.

Innovating out of the downturn 4/23/2009

GUEST OPINION: If history is any indicator, innovation, not the business cycle, will pull the semiconductor industry out of recession. But this time young, innovative companies jumping on advanced processes may play a disproportionate role.
DesignIdeas

Save valuable picoseconds using ECL-wired OR 5/15/2008

Substituting wire-OR connections for an XOR/XNOR ECL gate allows the circuit to meet stringent timing contraints.

CPLD connects two instruments with half-duty-cycle generator 10/11/2007

A clocking circuit programmed into a CPLD generates a synchronizing pulse for a slower instrument at half the duty cycle of a faster instrument.

VHDL program enables PCI-bus-arbiter core 9/13/2007

A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters.

Use SystemVerilog for coverage metrics 3/29/2007

SystemVerilog constructs suit RTL design, high-level modeling, testbench creation, and assertion specification.
ADVERTISEMENT

Events

46th Design Automation Conference

Dates: 7/26/2009 - 7/31/2009
Location: San Francisco, CA

Distinguished Speaker Lecture Series featuring Dr. Jeannette M. Wing, assistant director of the National Science Foundation

Dates: 7/28/2009 - 7/28/2009
Location: Design Automation Conference, Moscone Center, San Francisco

Freescale Technology Forum 2009

Dates: 9/2/2009 - 9/3/2009
Location: Hotel Leela Palace, Bangalore

Silicon Chip Training Seminar

Dates: 9/7/2009 - 9/7/2009
Location: Kensington, London

7th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Dates: 11/4/2009 - 11/5/2009
Location: Newport Beach, CA


EDN TECH CLIPS


Starting with the basics of PWM (pulse width modulation) counters, this clip discusses their usefulness in multiple applications and  demonstrates how to implement a PWM counter in an FPGA. Presented by Shelley Gretlein of National Instruments.; FPGA; national instruments; PWM counter; tutorial; video design idea; Using an inexpensive buck converter and a red LED, you can employ optical feedback to stabilize the output level of a high-intensity LED.; buck regulator; led; video design idea; Metastability of digital circuits can become a problem if you don't properly account for setup and hold times in synchronous circuits, or at random in the case of asynchronous inputs. Presented by Scott Davidson, Tektronix. ; asynchronous; setup and hold time; synchronous; Tektronix; video design idea; Dhananjay V Gadre of the Netaji Subhas Institute of Technology in New Delhi, India, details and demonstrates the use of "Charlieplexing" to drive 20 LEDs using six available I/O pins on an 8-pin microcontroller.; AVR; led; microcontroller; Tiny13; video design idea; Dhananjay V Gadre of India's Netaji Subhas Institute of Technology explains how an LED can double as a photosensor and a visual indicator of ambient-light intensity.; EDN.com; led; microcontroller; sensors; video design idea; Bonnie Baker, senior applications engineer at Texas Instruments and regular EDN columnist, demonstrates a simple way to add DAC functionality to a microcontroller-based system using only an op amp and two passive components.; analog design; Bonnie Baker; DAC; EDN.com; op amp; video design idea; Mark Thoren, mixed-signal application engineering manager with Linear Technology, demonstrates an amplifier-based circuit design for a relatively inexpensive precision voltage source.; amplifier-based circuit design; linear technology; Mark Thoren; mixed-signal application; precision voltage source; Jim Williams, staff scientist with Linear Technology, explains why PC clocks are invariably wrong, and how engineers can surmount the extreme measurement challenge involved in solving the problem.; cell phones; computer clocks; jim williams; linear technology; nanoamps; quartz crystals; video design idea; Dhananjay V. Gadre from New Delhi, India:
Demonstrating a battery-less electronic dice, made using a faraday voltage generator, an AVR Tiny13 microcontroller and 7 blue LEDs.; AVR; electronic dice; Faraday Generator; microcontroller; shake shake generator; Tiny13; EDN Tech Clips deliver technical depth and tutorial design information for engineers involved in analog circuit design, power management, embedded-system design, board-level design, signal integrity, and more. 
http://link.brightcove.com/services/link/bcpid27475330001 http://www.brightcove.com/channel.jsp?channel=959007201

Blog

Practical Chip Design

Memcon panel explores low-power main-memory choices

Following an active panel on DDR3 DRAM, last week's Denali Memcon offered up a second panel topic: low-power memory design. That's a wide enough to... 

Altera spins Cyclone with low-power, design protection, and redundancy

One sure indication that low-power FPGAs are beginning to penetrate the domain of small ASICs in power-constrained applications is that the FPGA ve... 

Mentor upgrades Catapult-C to deal with control logic and power management

Many—maybe even most—SoC design teams use C or C++ to explore algorithms and the behavior of their system before they begin implementat... 



Reed Business Information Resource Center

Featured Company


Most Recent Resources

ADVERTISEMENT


Technology Quick Links

EDN Marketplace



©1997-2009 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy

Please visit these other Reed Business sites