News
Team hardens SiGe circuits 11/12/2009
Manufacturers once aimed certain process technologies at radiation-hardened designs. CMOS, for example, started out that way, when RCA (www.rca.com) developed its silicon-on-sapphire process. However, the overwhelming success of bulk-silicon CMOS processes has driven most of the alternatives into niches, forcing up their cost to the point that only the best-funded programs can use an alternativ...Digital photomultipliers challenge vacuum-tube photomultipliers 11/12/2009
Despite massive improvements in solid-state light sensors in recent years, the detection of extremely low light levels has remained stubbornly resistant to the incursion of solid-state devices. The problems have been how to deal with the excessive dark count once you integrate the photodiodes into a circuit and how to reduce the cost of the specialized processes that the diodes require.Mentor assembles a test-yield fusion platform 11/2/2009
A pair of new yield-analysis tools kicks off a new fused test and yield product line.Intel, Numonyx to describe stackable phase-change memory array 10/28/2009
Eliminating a diode from the cell, researchers develop a memory that lives entirely in the interconnect stack.Fujitsu launches USB 3.0-to-SATA-bridge chip 10/8/2009
Fujitsu Microelectronics recently announced a 3.0-to-SATA (serial-advanced-technology-attachment)-bridge chip. The company intends the device to act as a connection between a USB (Universal Serial Bus) 3.0 cable and a SATA external-storage device.In-Depth
Debugging FPGA designs may be harder than you expect 10/22/2009
Bugs can originate at every stage in the FPGA design flow; debugging success depends on using the right tools and methods.Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces 10/15/2009
A new, all-digital approach to implementing high-speed PHY logic and a DLL offers a path to addressing increasingly stringent market requirements.IP quality lies beyond compliance testing 10/8/2009
Of course you want your standard-interface IP to pass compliance testing. But that accomplishment is just the beginning. Complete quality assurance for IP cores has far more challenges.FPGA architectural power-saving techniques at 40 nm 9/23/2009
As geometries shrink, FPGAs must begin to employ design-specific power-management techniques in order to save power while meeting timing.Outsourcing an IC design: Some advice from the trenches 9/3/2009
In this climate, outsourcing is becoming a mandatory skill for IC-design managers. But it's not intuitively obvious.Experts
Boeing postpones test flights again: How’s your tapeout looking? 11/12/2009
Boeing's recent issues offer a cautionary tale for any chip-design team engaged in a complex project.Reference-tool flows and process-design kits, part two 11/12/2009
As a result of the shift to global design centers and the reduction in time designers spend on each process node, it is no longer always accurate to assume that experienced designers will be working with PDKs.Openness and cooperation create healthy EDA ecosystem 9/29/2009
GUEST OPINION: Competition brings progress, but it helps the customer only if we respect standards and the need for interoperability.Reference-tool flows and process-design kits, part one 9/17/2009
Reference-tool flows and process-design kits have been the basis of chip design since the start of the semiconductor industry. Although these files provide adequate information, they alone do not represent all of the issues.SOI Industry Consortium stalks the “green thing” 8/20/2009
In some cases, the semiconductor's appeal to greeness makes sense, even without adding chlorophyll to the package epoxy.DesignIdeas
