;*********************************************************************************
; di2465.txt
;
; LISTING 1 - VERILOG DESCRIPTION OF THE SYNCHRONIZED ASYNCHRONOUS-RESET CIRCUIT
;
; "Synchronous asynchronous reset," EDN, Jan 6, 2000, pg 128
; http://www.ednmag.com/ednmag/reg/2000/010600/designideas.htm#01di5
;*********************************************************************************

module reset (clk, irst_n, orst_n); 
// Willy Tjanaka
// Rev. 1.0, 17 October 1999  
input  clk, irst_n;
output orst_n;
reg    orst_n, mrst_n;
always @ (posedge clk or negedge irst_n)
begin
  if (!irst_n)
  begin
    mrst_n <= 1'b0;
    orst_n <= 1'b0;
  end
  else
  begin
    mrst_n <= irst_n;
    orst_n <= mrst_n;
  end
end
endmodule