;******************************************************
; Listing 9 -- Instantiating the counter of Listing 8
;              in a top-level entity
; "10 tips for generating reusable VHDL,"
; EDN, August 19, 1999, pg. 49
;******************************************************

architecture inst of top is begin signal my_count : std_logic_vector(7 downto 0);
signal clk, reset_n : std_logic;
cnt: counter port map
  ( clk => clk,     reset_n => reset_n,
    count => my_count
  );
..
..
..
end inst;