Resistive DAC and op amp form hybrid divider
A resistive DAC in a resistivefeedback loop of an op amp lets you create an analogdigitalanalog divider. The resistance, R_{WA}, between the W and A terminals of the Analog Devices AD5293 (Figure 1) decreases linearly with increasing the digitalcontrol data, D:
and the value of the R_{WB}, the resistance between the W and B terminals of the DAC, rises proportionally to D as
R_{AB} is a constant value of resistance between the ends of the digital potentiometer. The circuit uses resistance R_{WA} as a feedback resistor, and resistance R_{WB} connects between the inverting input of the op amp and ground. The voltage gain of the noninverting amplifier becomes
The output voltage is
Both the input voltage and the digitalinput data can be time variables, and the clock frequency for fetching digitalinput data can be as high as 50 MHz.

The potentiometer's data sheet provides the groundreferred parasitic capacitances at the A, B, and W terminals of the potentiometer. Thorough measurement of the capacitances at these terminals provides enough data to determine capacitances between the terminals. An evaluation of the measured data shows that the direct capacitance between the A and W terminals at the midscale position of the wiper is just 2.4 pF:
If you assume that the five segments of the potentiometer are ordered topologically into a chain, then the direct intercapacitance between the A and B ends of potentiometer is
The capacitance per segment of the five segments of the potentiometer is
where X=½ denotes the midscale of the resistive DAC.
The fivestep distributed RC line of the potentiometer has a time constant of
where R_{AB} is 20 kΩ. The groundreferred wiper capacitance, C_{W}, of 40 pF is much higher than the intercapacitances and creates a time constant:
The feedback network of the amplifier is frequencycompensated for τ_{SEGM}≃τ_{W}. Thus, you can calculate the value of R_{WB} as 600Ω, meaning that the voltage gain of the amplifier, A_{V}, is 32.3. For gains higher than 32.3, the effect of C_{W} becomes negligible, and you need not bother about amplifier stability. To suppress the derivative behavior of the amplifier for gain values of two to 32.3, you can add a 40pF compensating capacitor in parallel to feed back part of the potentiometer. The amplifier thus has an integrating character for all gains down to a value of two.
You fetch the divisor, Y, which is a digitaldata word, D, through a standard SPI (serialperipheral interface). After poweron, you must initially neutralize the writein protection of the resistive DAC. You have to first program the control bit C_{1} to the value of one, whereas it is zero by default. You achieve this task by clocking in the word containing C_{3}, C_{2}, C_{1}, and C_{0}, which equals 0110, and you put the desired C_{2} and C_{1} values at data positions D_{2} and D_{1}. After performing these steps, you change the wiper position in which the control bit is C_{3}, C_{2}, C_{1}, and C_{0}, which equals 0001, and the data bits, D_{9} to D_{0}, represent the gain as 1024/D.
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