Current limiter allows large USB bypass capacitance

Daniel Morris, Group IV Technology, Renton, WA; Edited by Martin Rowe and Fran Granville -August 06, 2009

The USB (Universal Serial Bus) specification requires a connected USB device to present a load to the host or hub of no greater than 10 µF in parallel with 44Ω, including the effects of any bypass capacitance visible through the device’s voltage regulator. This limit avoids excessive voltage drop at the device as inrush current charges its capacitance. Occasionally, a bus-powered device needs more than 10-µF bypass capacitance to provide an adequate reservoir for current spikes. The circuit in this Design Idea repurposes a Linear Technology LTC6102 precision current-sense amplifier, IC1, to limit inrush current below the specified maximum, allowing the device to use more capacitance when necessary.

The LTC6102 usually translates the voltage across a current-sense resistor to a larger ground-referenced voltage in an output resistor. The part features an amplifier with low offset voltage, letting you use low-value sense resistors. In the usual circuit configuration, output current flows through an onboard FET whose source connection connects to a force pin separate from the amplifier input pin to minimize errors across trace and pin resistances.

This circuit grounds the LTC6102’s output pin and uses the onboard FET as a source follower to drive the gate of an external current-limiting FET (Figure 1). The feedback loop around the LTC6102 maintains equal voltages at the positive and negative inputs of the amplifier, pins 8 and 1 of IC1. Resistor divider R2/R4 sets the positive input of the amplifier, IC1’s Pin 8, approximately 2 mV below the 5V USB-voltage rail. With Q1 initially off at device connection, the negative amplifier input, IC1’s Pin 1, is higher than the positive input, causing the amplifier’s output to go low. As the amplifier’s output drops, the onboard FET follows, pulling the gate of Q1 low and turning it on. Current increases in Q1 until the voltage drop across sense resistor R1 matches the drop across resistor R2.

Figure 1 This circuit limits USB-device current both at connection and after configuration.

Resistor R3 and capacitor C2 compensate the feedback loop against oscillation and slow the turn-on of Q1, preventing an initial current spike when the device connects to the bus. Capacitor C3 bypasses a regulator on IC1. Resistor R7 meets the allowed maximum 1-mA current through the FET on IC1. Q1 turns on at a gate voltage low enough that it does not exceed the input range of 4V positive voltage to IC1’s Pin 7 to Pin 2.

Instead of the large capacitive load of C1, the circuit presents a resistive load to the USB host equal to R1(R2+R4)/R4=49.8Ω, lighter than the 44Ω maximum requirement. After C1 charges, the circuit continues to limit current below the 100-mA maximum permitted to a low-power USB device. Upon configuration, the device can raise the current limit to the 500-mA maximum permitted to a high-power device by turning on FET Q2 to place R5 in parallel with R4, increasing the voltage maintained across sense resistor R1.

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