# Start with the right op amp when driving SAR ADCs

Click here to download a PDF |

SAR (successive-approximation-register) ADCs (analog-to-digital converters) are playing an increasingly prominent role in the design of highly effective data-acquisition systems for automatic test equipment, instrumentation, spectrum analysis, and medical instruments. SAR ADCs make it possible to deliver high-accuracy, low-power products with excellent ac performance, such as SNR (signal-to-noise ratio) and THD (total harmonic distortion), as well as good dc performance.

For optimum SAR-ADC performance, the recommended driving circuit is an op amp in combination with an RC filter (**Figure 1**). Although this circuit commonly drives ADCs, it has the potential to create circuit-performance limitations. If you don’t properly select the input resistor, R_{IN}, and the input capacitor, C_{IN}, values, the circuit could produce ADC errors. Worse yet, it could cause the amplifier to become unstable. If you ignore the op-amp open-loop output impedance and UGBW (unity-gain bandwidth), you may run into amplifier-stability issues.

The optimized ADC-driver circuit in **Figure 1** uses an op amp to separate the ADC from high-impedance signal sources. The following RC lowpass filter, R_{IN} and C_{IN}, performs functions going back to the op amp and forward to the ADC. R_{IN} keeps the amplifier stable by “isolating” the amplifier’s output stage from the capacitive load, C_{IN}. C_{IN} provides a nearly perfect input source to the ADC. This input source tracks the voltage of the input signal and charges the ADC’s input sampling capacitor, C_{SH}, during the converter’s acquisition time.

In evaluating the circuit in **Figure 1**, you can determine the guidelines and constraints for selecting the value of R_{IN}. The op amp’s open-loop output resistance, R_{O}, and the UGBW or the unity crossover frequency, f_{U}, as well as the value of C_{IN}, govern this issue (**Reference 1** and **Figure 2**). After defining the design formulas for R_{IN}, you can determine the value of C_{IN}. The ADC’s acquisition time and input sample-and-hold capacitance, C_{SH}, as well as R_{IN}, influence the value of C_{IN}.

Once you understand how this circuit operates, you can establish the criteria for a stable system and define an appropriate design strategy. A proof of concept uses two sample circuits. The first is relatively stable; the second is marginally stable.

**Op-amp stability with R**

_{IN}and C_{IN}The ADC in **Figure 1** cycles through two stages while converting the input signal to a digital representation. Initially, the converter must acquire the input signal. After acquiring the signal, the converter changes the sampled information, or “snapshot,” of the input signal to a digital representation. A critical part of this process is to obtain an accurate snapshot of the input signal. If this ADC-data-conversion process is to run smoothly, the driving amplifier must charge the input capacitor to the proper value and maintain stability during the ADC’s acquisition time.

You can determine the stability of an amplifier with a Bode plot, a tool that helps you approximate the magnitude of an amplifier’s open- and closed-loop-gain transfer functions. In **Figure 2**, the units along the Y axis describe the gain in decibels of the amplifier in **Figure 1**. The units along the X axis describe the frequency in log, hertz of the open- and closed-loop-gain curves.

If the closure rate of the closed- and open-loop-gain curves is greater than 20 dB/decade, the amplifier circuit will be marginally stable or completely unstable. For example, if the open-loop-gain curve, A_{OL}, is changing at –40 dB/decade, the amplifier circuit is unstable where the slope of the closed-loop-gain curve, A_{CL}, is zero at the intersection with the open-loop-gain curve.

You can evaluate the stability of the circuit in **Figure 1** with the op amp’s open-loop-gain function, A_{OL} (**Figure 2**). The amplifier’s dc open-loop gain is 120 dB. At approximately 7 Hz (f_{0}), the op amp’s open-loop curve leaves 120 dB and progresses down at a rate of –20 dB/decade. As the frequency increases, this attenuation rate continues past 0 dB. The open-loop-gain curve, A_{OL}, crosses 0 dB at approximately 7 MHz (f_{U}). Because this curve represents a single-pole system, the crossover frequency, f_{U}, is equal to the amplifier’s UGBW. This plot represents a stable system because the closure rate of the closed- and open-loop-gain curve is 20 dB/decade.

**Figure 3** provides an accurate picture of the amplifier’s performance minus the ADC’s impact. Introducing the external RC on the op amp’s output modifies the amplifier open-loop-gain curve.

System level design and integration challenges with multiple ADCs on single chip

Understanding the basics of setup and hold time

Product How-to: Digital isolators offer easy-to-use isolated USB option

Managing noise in the signal chain, Part 2: Noise and distortion in data converters

War of currents: Tesla vs Edison

Simple reverse-polarity-protection circuit has no voltage drop

Control an LM317T with a PWM signal

Start with the right op amp when driving SAR ADCs

Currently no items