Voltage-mode control and compensation: Intricacies for buck regulators
By Timothy Hegarty, National Semiconductor - June 30, 2008
It would be a masterpiece of understatement to suggest that control loop compensation holds much significance in power converter design. This is true in part because of increasing demand for ultra-fast load transient dynamic response—especially with voltage regulator modules (VRMs) targeted at the VCORE applications (Reference 1)—and in part because of concerns for loop stability and its direct implications for product robustness and reliability. It is also true that the burgeoning popularity, perceived advantages and abundant methods of current mode control (CMC), including peak, valley, average and emulated inductor current techniques (Reference 2) or hybrid schemes like enhanced V2 control (Reference 3), have diverted focus from traditional voltage mode control (VMC) as the loop control methodology prevalent in DC-DC power conversion. This may have emanated from the conventional wisdom that when compensating voltage mode converters, more design choices are necessary and significant a priori knowledge and design know-how are required to extract an optimum design.
The theme of this article seeks to examine the particulars of voltage mode control as applied to output voltage regulation in buck or buck-derived converter topologies. First and foremost, the power and control stages are reviewed with respect to the small-signal model and relevant transfer functions. It is demonstrated how the crossover frequency of the loop gain is significant in the context of the frequency range where feedback is effective in attenuating the closed-loop characteristics, such as output impedance and audio susceptibility. Control loop compensation is described with heuristic analysis and design procedure. It is revealed that the multiple design iterations and somewhat complicated component selection procedures hitherto proposed and commonly employed with voltage mode compensation analysis and design can be simplified to the extent that, from a user perspective, the essence of single-loop voltage mode control can be considered relatively straightforward and intuitive vis-à-vis multiloop current mode control.
More particularly, the merits and demerits of fully integrated, partially integrated and fully external compensation components are distilled in the context of ease of design and flexibility with IC type PWM controllers and regulators. To this end, specific examples of practical implementations with monolithic CMOS regulator ICs as well as a BiCMOS controller IC based solution, all from National Semiconductor, are underscored to conclude the discussion.
Buck converter power and control stage review
The generalized schematic of a single phase/channel synchronous buck converter using voltage mode control and a type III compensation circuit is embodied in .
Non-ideal power train components are shown in the foregoing schematic with parasitics such as inductor DC resistance, RDCR, and capacitor equivalent series resistance, RESR, denoted explicitly. Second order parasitics, such as capacitor equivalent series inductance (ESL) and interconnection impedances, are not represented. The high side switch is driven by a PWM signal for time ton in each switching period of duration Ts. The duty cycle ratio D is given by
The low side switch is driven complementarily with duty cycle D' = 1 – D. Both switches operate at fixed switching frequency ƒs = 1/Ts. The output filter consists of inductor LO and capacitor CO. For simplicity, the driver and deadtime generation stage with associated logic are denoted in block format.
A conventional op-amp type voltage error amplifier represents the epicenter of the control loop structure. The divided down output voltage at the error amplifier inverting input, usually termed the feedback (FB) node, is compared to a fixed reference voltage, Vref, and a compensated error signal is generated at the compensation node, labeled COMP. This error signal is compared to a saw-tooth ramp voltage at the pulse width modulator (PWM) comparator such that an increase in COMP leads to a commensurate increase in duty cycle command for the power stage. Trailing-edge modulation is underlined herein whereby a turn-on command is activated at the clock edge and a turn-off command is imposed when COMP intersects the ramp voltage. Alternative PWM strategies chronicled in the technical literature include leading-edge and double-edge modulation.
Buck converter small-signal analysis
The appropriate small-signal average model (Reference 4) for the single- (and multi-) phase buck converter circuit is manifested in . Using standard averaging and linearization techniques around a DC operating point, the small-signal duty cycle perturbation, designated in the Laplace domain, effectuates a resultant linear variation in output voltage, . Four small-signal functions of the loaded power converter system are of salient importance:
PID compensator transfer function;
closed-loop line-to-output transfer function;
closed-loop output impedance.
These parameters are easily derived from the small-signal model and are given respectively by equations 2 to 5, where CO is the output capacitance value (appropriately derated for applied voltage and operating temperature), RL is the effective load resistance and RDAMP is the total series damping resistance associated with the inductor DCR, power FET RDS(ON) and PCB trace resistance.
Although the loop gain is of primary importance, a regulator is not specified directly by its loop gain, but by its performance related characteristics, namely closed-loop output impedance and line-to-output transfer function.
Open loop transfer function
The open-loop control-to-output voltage transfer function in the Laplace domain is given by equation 2, or more succinctly in its normalized form by
Evidently, the power stage transfer function of a voltage mode buck converter has a complex double pole related to the LC output filter and a left half plane zero due to the output capacitor ESR, the locations of which are given respectively by
fo and fESR represent the LC filter complex double pole and output capacitor ESR zero, respectively.
The PWM modulator gain, FM, is inversely proportional to the peak-to-peak ramp voltage, and given by
Error amplifier finite gain-bandwidth notwithstanding, the compensator transfer function from output voltage to COMP node given by equation 5 can be more aptly written as
The type III compensator produces three poles and two zeros. One pole is located at the origin to realize high DC gain while the frequencies of other singularities—signified by red (pole) and blue (zero) dashed rings surrounding the relevant components in —are determined by component values as follows
The open-loop transfer function of the system, denoted by Tv(s) in , measured by breaking the loop, injecting a variable frequency oscillator signal and recording the ensuing frequency response using a gain-phase analyzer setup, is given by
shows a bode plot of the loop gain and phase of a typical system. The poles and zeros of the system are marked with × and o symbols respectively, and a + symbol indicates the bandwidth at crossover. and typify the individual gain and phase characteristics of the LC filter, modulator and compensator.
The open-loop output impedance in the Laplace domain, Zo(s), is the parallel LCR impedance looking back into the output filter and load given by equation 3, or more succinctly in its normalized form by
Here, it is assumed that the duty cycle perturbation is zero with no feedback control. The parameter ωL = LO/RDAMP is the inductor zero frequency and ZL(s) = RDAMP + sLO. The open-loop output impedance is limited by the parasitic resistance RDAMP at low frequency and the output capacitor at high frequency. The closed-loop output impedance can be derived from the small-signal block diagram in and corresponds to the open-loop impedance divided by the feedback factor [1+TV(s)], i.e.
This coincides with the usual properties of single-loop feedback systems. The importance of the loop gain is now apparent and the relationship between loop gain and closed-loop parameters is generally intuitive in single-loop systems. Consider the case where a current Iout represents the nominal load current and is a source of perturbation. If is a step function, the corresponding is the system step response governed by ZoCL(s). Thus, ZoCL(s) provides an assessment of the output voltage response to a load current transient demand.
Two salient points are noteworthy: (a) the output impedance of the regulator should be much less than the load impedance and (b) the effective "bandwidth" of the output impedance should be much larger than the bandwidth of the load to achieve fast recovery from load transients. illustrates the open- and closed-loop output impedance of a typical system. The difference between the open- and closed-loop responses is effectively the loop gain and the two plots converge within 3dB of each other at the loop gain crossover frequency, denoted by the + symbol in . Note that no additional attenuation is achieved at higher frequencies by closed-loop feedback.
Line disturbance rejection
The open-loop line-to-output transfer function—also termed power supply ripple rejection (PSRR) or audio susceptibility—is defined as the transfer function from perturbation of the input voltage to perturbation of the output voltage with duty ratio held constant. This transfer function, Gvg(s), given in the Laplace domain by equation 4 contains the same poles and zeros as Gvd(s) and can thus be written in its normalized form as
Again, it is assumed the duty ratio D is fixed with no AC variation, i.e. no feedback control. The closed loop line-to-output transfer function can be obtained (in similar fashion to the aforementioned closed loop output impedance) as
By evaluating the loop gain and making it as large as possible and with high bandwidth, the open-loop audio susceptibility can be largely attenuated by closed-loop operation right up to the bandwidth of the loop gain. shows the open- and closed-loop audio susceptibility characteristics of a typical system. The closed-loop parameter has particular significance in terms of line regulation when a 100/120-Hz signal is superimposed on the converter input or when the input to a point-of-load buck converter (POL) is connected to the output of an unregulated intermediate bus converter (IBC) as part of a distributed power architecture.
Buck converter VMC compensation design
The conventional compensation strategy (References 5 and 8) employed with voltage mode control is to use two compensator zeros to counteract the LC double pole, one compensator pole located to nullify the output capacitor ESR zero and one compensator pole located at one half switching frequency to attenuate high frequency noise.
fz1 = fz2 ≤ fo ;
fp1 = fESR ;
fp2 = fs/2 ;
Finally, a resistor divider network from Vout to FB determines the desired output voltage. Note that the lower feedback resistor, RFB2, has no impact on the control loop from an AC standpoint since the FB node is the input to an error amplifier and effectively at AC ground. Hence, the control loop can be designed irrespective of output voltage level. The only caveat here is the necessary derating of the output capacitance with applied bias voltage.
The loop gain crossover frequency, ƒc = ωc/2π, is usually selected between one tenth to one fifth of the switching frequency. Bearing in mind that the pole located at fp1 cancels the zero located at fESR and the pole at fp2 is located well above crossover, the expression for Tv(s) specified by equation 13 and more explicitly by equation 18 can be manipulated to yield the simplified expression given by equation 19.
Essentially, a multiorder system is reduced to a single order approximation by judicious choice of compensator components. portrays a comparison of the exact and approximate loop gains expressions presented in equation 18 and equation 19, respectively, using a typical converter circuit. Excellent correlation is obtained at low frequency and around crossover when the compensator singularities are located as described.
Regularly, the value of RC2 is much less than RFB1, particularly with ceramic output capacitors where the resultant ESR zero is located at high frequency. Realizing that , a simple solution for the crossover frequency with type III voltage mode control is derived from equation 19 as
Knowing the desired location of the compensator poles and zeros, values for RC2, CC1, CC2 and RFB1 can be calculated from the design-oriented expressions in equation 21 based from those in equation 12, assuming an initial value is selected for RC1. RFB2 is then selected based on the desired output voltage.
Referring again to the system bode plot in , the phase margin, indicated as M, is the difference between the loop phase and –180°. A target of 50° to 60° for this parameter is considered ideal. Indeed, for a second order system with single-loop control, phase margin is directly related to transient response and a phase margin of 52° results in closed loop-peaking factor Qo of unity (Reference 4). More phase margin can be dialed in by locating the compensator zeros at a frequency lower than the LC double pole.
Buck converter IC implementations
There has been a range of CMOS buck regulator parts recently offered by semiconductor manufacturers that advantageously incorporate the power MOSFETs, driver stage and control loop section to achieve a high density power supply solution. To attain even higher density and lower component count, some or all of the control components are integrated into the IC. Generally, given a semiconductor process, a lot of work is focused on producing the smallest area circuit. Knowing that chip area comes with a premium cost, capacitive component fabrication is problematic—capacitors with a large energy storage requirement will use an excessive amount of die area. This places a limitation on the compensation capacitor value. Other key considerations when appraising a particular regulator IC implementation are as follows:
access to the COMP node for power supply characterization, bode plot measurement, soft-start or enable functions;
line feedforward and associated complexity;
flexibility, ease-of-use, filter inductor and capacitor limitations;
component count, reliability;
component footprints, PC board real estate requirements;
integrated compensation component initial tolerance and temperature coefficient.
and illuminate examples of low voltage (2.95V to 5.5V input voltage range) CMOS buck regulator implementations from National Semiconductor (Reference 5 and 6) with fully integrated and partially compensation components, respectively.
The LM2853 has all the classic type III compensation components incorporated internally, including output voltage setpoint resistors. This creates a high density solution with low parts count and reduced pick-and-place operations during automated SMT manufacturing process. However, unlike the LM2854, the LM2853 implementation generally has no option to pursue high bandwidth closed-loop performance or optimum transient response. This stems from the realization that a conservative loop design is necessary to accommodate a broad range of output filter components.
The LM2854 has internal type II compensation components located around the error amplifier between FB and COMP. These are designed to locate a pole at the origin and a pole at half switching frequency. Furthermore, a zero is located at 8.8 kHz or 17.6 kHz for the 500 kHz or 1 MHz switching frequency options, respectively, to approximately cancel the most likely location of one LC filter pole. The three external compensation components, RFB1, RC and CC, are easily selected by simple design expressions to position a zero at or below the LC pole location and a pole to cancel the ESR zero.
shows an example of a buck converter using a LM3743 BiCMOS voltage mode PWM controller IC (Reference 7). In addition to the output voltage setpoint resistors, the five components that embody type III compensation are discrete parts, usually realized with 0402 or 0603 size surface-mount passives. These components are user-defined and facilitate maximum flexibility with the control loop design and implementation. To this end, the availability of compensator design software from IC vendors can greatly assist in the compensation component selection process. The power supply designer then has all the tools at his/her disposal to optimally position the loop crossover frequency while maintaining adequate phase margin over the required power supply line, load and operating temperature ranges.
Timothy Hegarty is a staff applications engineer in National Semiconductor ’s Infrastructure Products Power Management Group in Tucson, AZ, where he is primarily responsible for new product evaluation, applications, and customer design tool development. He received his bachelor's and master of science degrees in electrical engineering in 1995 and 1997 from University College Cork in Ireland.
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