Buffer adapts single-ended signals for differential inputs
DC coupling of single-ended signals into differential-input, single-supply ADCs can be challenging. The input signal requires level shifting from ground to VS/2 as well as single-ended-to-differential conversion. In addition, you must balance the differential inputs of the ADC to cancel even-order harmonics and common-mode noise. Systems often require this signal translation to take place without injecting dc bias currents back into the signal source. Processing wideband signals with large dynamic range (12- to 14-bit ADCs) can also add to the circuit complexity. Wideband amplifiers address nearly all these issues, but their standard implementation requires the use of ac coupling.
This Design Idea describes a new circuit that eliminates this requirement through the use of an external dc feedback loop. It also allows the lower end of the passband to extend to dc. The basis of the circuit is a simple level-shifting circuit (Figure 1). Tying two series resistors between VS and a signal source attenuates the signal by a factor of two and biases it to VS/2. The center tap is buffered; single-sided supply circuits can then process the signal. Two additional series resistors connected between the source and a negative supply of equal value remove dc bias currents from the source.
The circuit of Figure 2 expands upon this simple concept by replacing the supply voltages ±VS with precise ±VDClevels that track one another. In addition, this design implements differential signaling by doubling the number of level-shifting resistors. You produce the ±VDC levels by subtracting the 2.4V ADC reference signal (CML pin) from the common-mode level of the amplifier, which you form by summing the two amplifier outputs through equal-value resistors. The circuit amplifies, filters, and inverts the difference to create the ±VDC levels. The dc feedback-loop gain of approximately 1040 allows the amplifier to track the output common-mode level to within (2.4V/1040)=2.3 mV of the ADC's reference (CML) signal. The addition of this external dc feedback path allows you to open the VOCM pin of IC1 and decouple it to ground, disabling the AD8351's internal dc feedback path.
The level-shifting resistors have a ratio of 1.09-to-1 to reduce the required swing of the ±VDC levels to ±2.4 [(1.09+1)/1.09]=±4.6V. The design uses accurate networks with excellent tracking to ensure good CMRR (common-mode-rejection ratio) and minimize the injection of dc bias currents into the source. IC2 uses a rail-to-rail feedback amplifier to allow the use of ±5V supplies. The remaining circuits are powered from 5V. Resistor RG varies the overall gain of the front end. For a front-end gain of 0 dB, the bandwidth extends beyond 1 GHz (Figure 3). After you determine the required gain, you adjust resistor RF to balance the two differential signals into the ADC. Table 1 shows typical values of RG and RF for various gain levels. The 64.9Ù resistor provides for a 50Ù source impedance. The 28Ù resistor provides for a balanced input that the amplifier sees. You can accommodate a differential-input signal structure by replacing the 28Ù resistor with a 64.9Ù resistor and tying the additional negative input signal to the junction of the new 64.9Ù resistor and the two 240Ù level-shifting resistors. This differential-input structure allows you to remove RF. The circuit maintains the excellent distortion performance of the AD8351 amplifier, allowing the circuit to drive 12- and 14-bit ADCs with minimal degradation of the ADC's dynamic range (Figure 4).
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