Circuit provides hiccup-current limiting

-June 26, 2003



Current-limit protection is an essential feature for power-supply systems. The three major types of current-limit-protection mechanisms are constant, foldback, and hiccup. Hiccup current limit performs the best of the three types; however, the implementation is rather complex. In this scheme, upon detection of an overcurrent event, the whole power supply shuts down for an interval before it tries to power itself up again. The cycle repeats until the overcurrent fault disappears. With such operation, the dissipation in the power supply itself is minimal. You can incorporate the circuit in

Figure 1a

into the PWM circuit of a switch-mode power supply to implement the hiccup feature.

Figure 1b

represents a typical shunt-voltage regulator to regulate the VCC that powers the PWM controller.

Most PWM controllers have an undervoltage-protection feature, in which the internal circuitry shuts down whenever its VCC drops below a certain threshold. For example, assume that the circuit in

Figure 1a

works with a UCC3570 PWM controller. In this chip, an excessive current that causes the Count pin to exceed 4V or the ILIM pin to exceed 0.6V sets the shutdown latch. This action then forces the PWM controller's output to go low and discharge the soft-start capacitor, C2. The discharge current of C2 causes Q3 and, hence, Q2 to turn on for a short interval to charge the timing capacitor, C1. The moment the voltage across C1 builds up, Q1 turns on and activates IC1 to overwrite the VCC voltage, which DZ initially set to a voltage—in this case, 7.02V—low enough to turn off the PWM controller (

Figure 1b

). With this action, the controller becomes temporary disabled, and the shutdown latch resets.

After C2 completely discharges, Q3 and Q2 switch off, and the charge stored in C1 continuously supplies the base drive needed to hold Q1 on through R1. The PWM controller then stays in sleep mode for the fixed interval, tSLEEP, until the discharge current of C1 can no longer keep Q1 on. You can estimate this sleep-time interval (Figure 2) by using the following equation:

where IIC1 is the forward current of IC1 (10.7 mA with VAUX=12.5V), VC1(0) is the initial voltage stored in C1 (5.05V), τ=R1C1 (1.1 sec), hFEQ1 is the dc current gain of Q1 (170 from test results), and tSLEEP is the sleep time for the PWM IC (2 sec).

Note that, according to the 2N2222A data sheet, dc current gain can be 75 to 300. Therefore, to obtain a better prediction from the above equation, it is advisable to determine the dc gain through simple testing. To solve the equation, you must first determine VC1(0). This quantity depends on several factors. First, it depends on the PWM IC. The IC can discharge the soft-start capacitor either linearly (constant-current sink) or exponentially (RC discharge). Knowing this fact, you can work out the turn-on time, tON, of Q3 and Q2 by plugging tON and VCC into the standard RC-charging equation with the time constant of τ1=R2C1. In Figure 1a, because 2.3τ1ON&5τ1, you can approximate VC1(0) by using VC1(0)=VIC1–VBEQ4–VCEQ2–VD1.

After time period tSLEEP elapses, C1 should have discharged to a low enough voltage to turn off Q1, thereby allowing VCC to climb back to its normal value, thus enabling the PWM controller. The soft-start capacitor then charges up again. The output pulse gradually starts to generate after the soft-start voltage reaches the internal threshold. This "sleep-reboot-detect" cycle repeats until the fault disappears.

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