Two DDS ICs implement amplitudeshift keying
Many communications systems, including RFID systems and cable modems, use AM (amplitude modulation). This Design Idea shows how two DDS (directdigitalsynthesis) devices can implement AM and ASK (amplitudeshift keying) over a range of frequencies. The AD9834 complete 50MHz DDS IC (Figure 1) has a current output, so you can easily sum the outputs of two or more of them by connecting them to a common termination resistor. Each AD9834 has two internal phase registers, P_{0} and P_{1}, and two internal frequency registers, F_{0} and F_{1} (not shown). With each AD9834 generating a sine wave at the same frequency, the amplitude of the summed signal depends on the phase of each signal. You can achieve four preset amplitude levels—or any onthefly level—by summing the outputs of two AD9834s.
Table 1 shows two AD9834s, IC_{1} and IC_{2}, configured to give four output levels. P_{0A} is phase register 0 for IC_{1}, P_{1A} is phase register 1 for IC_{1}, and so on. You can select the desired output level with either the PSEL pins or with the PSEL bits in the control register. Figure 2 shows the waveforms at the R_{TERM} summing junction for the phases used in Table 1. You can achieve any signal level from 0V to a fullscale voltage of approximately 600 mV by programming the phase registers with the appropriate values. Both devices use the same MCLK (master clock), and you need to synchronize them to get the correct signal levels at the R_{TERM} output. You achieve synchronization by simultaneously applying a Reset signal to both parts after programming both parts with the correct phase and frequency. You can accomplish the synchronization by applying a positive pulse to the Reset pins, or you can implement a software synchronization by setting the reset bit in the control register to one, stopping MCLK, setting the reset bit in the control register to zero, and then starting MCLK. Either method ensures that both parts simultaneously exit the reset state.
You can easily implement 100% AM with a single AD9834 by toggling the Reset pin or the reset bit in the control register. When the part is in reset, the DAC's output is at midscale. The predetermined sine wave is available at I_{OUT} when the DDS exits reset. To calculate the magnitude of the sum of the two signals from the AD9834s, represent each signal as a rotating vector (Figure 3). You can easily calculate the magnitude and phase of the resulting summed vector as follows: If the length of each vector is 1, then:

x1=Cos(45°)=0.707: y1=Sin(45°)=0.707;

x2=Cos(180°)=–1.00: y2=Sin(180°)=0;

x3=x1+x2=–0.293: y3=y1+y2=0.707;

Magnitude of resulting vector: =0.765;

Phase of summed vector: 112.5°(180°–Tan^{–1}(y3/x3)).
The maximum outputvoltage level that any one AD9834 can develop across the 100Ω termination resistor with R_{SET}=6.8 kΩ is 320 mV pp. Therefore, the voltage level this example achieves is 320 mV×0.765=244.8 mV. This example shows that the phase of the resulting summed vector depends on the phase of two input vectors and may result in a phase discontinuity as the phases of the input vector change. To avoid phase discontinuity at the transition, you can set the resultant phase, P3, to a fixed angle, say 180°≥p2=360°–p1.
Sin(2πf+p1)+Sin(2πf+p2)=2Cos(0.5(p1–p2))×Sin(2πf+(p1+p2)/2).
Desired amplitude: A=2Cos [0.5(p1–p2)]; p1–p2=2Cos^{–1}(A/2).
Resultant phase: P3=(p2+p2)/2.
Therefore, p1=180°+Cos^{–1}(A/2), and p2=180°–Cos^{–1}(A/2) gives amplitude A with no phase shift at the transition.
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