Envelope follower combines fast response, low ripple
Envelope followers extract amplitude information from complex audio waveforms. The resulting dc voltage often drives nonlinear stages, such as voltage-controlled amplifiers or filters. You must make a careful trade-off between the speed of response to a rapidly changing input signal and the amount of ripple in the dc output that you can tolerate. If the system is too slow, the output has low ripple but badly distorts the envelope shape. If it's too fast, ripple can modulate the nonlinear stages, causing audible distortion products. Audio sources, such as a guitar, pose special problems. The instrument has an attack of a few milliseconds and a long decay time. The musician may "mute" the strings at any time, causing the normal exponential decay to terminate abruptly. The waveform is sometimes unsymmetrical and may have multiple zero crossings. The fundamental frequency range is typically from approximately 80 Hz to 1.5 kHz. Previous circuits have used a full-wave bridge and a large averaging filter. A filter time constant sufficient to reduce ripple makes the circuit unable to follow rapid changes in amplitude. Peak-detecting circuits can follow the rapid attack and provide low ripple during the exponential decay but cannot follow the rapid decay of a muted string. The design in Figure 1 features fast attack and low ripple with minimal filtering, and it can follow a rapid decrease in signal (mute).
The circuit uses three identical peak-hold circuits in parallel that reset in a round-robin fashion. The circuit applies the input signal to all three stages simultaneously. As each stage resets in turn, the two remaining stages still hold the last peak voltage. Diodes select the highest held voltage at the output of each peak-hold stage. A small RC filter smoothes the step response as the peak-hold circuits reset, so a lower output voltage results. To ensure that one of the detectors holds the highest peak value for the entire input period, the reset clock period is slightly longer than one-half the period of the lowest input frequency. Figure 2 illustrates typical circuit operation and shows the improvement over full-wave average and peak-detecting circuits with similar time constants. CMOS Schmitt inverter IC1 forms the master reset clock, and C1 and R1 produce the desired period. CMOS counter IC2 is a ring counter that provides the sequential reset pulses. The peak-hold circuit is a classic configuration with the addition of the reset circuit. R2 and C2 differentiate the rising edge of the reset pulse; this edge drives the base of Q1. Series resistor R3 prevents excessive op-amp current while Q1 is conducting. The filter network comprising R4, R5, C3, and D1 provides minimal filtering to reduce the step changes in the output during unusually fast decay times.
Is this the best Design Idea in this issue? Select at www.edn.com.