Power-integrity simulation keeps your planes perfect, part 1
Paul Rako, Technical Editor - July 14, 2011
Delivering power to the chips on your PCB (printed-circuit board) is no longer a simple proposition. You used to be able to connect the ICs to power and ground using thin traces that took little space. As chips got faster, you fed them power with low-impedance sources, such as a power plane on your PCB. For a time, just using a power and ground plane on a four-layer board would solve most power-integrity problems. In addition to the power planes, you could decouple every IC to solve any niggling power problems with your design.
These days, though, PCB areas—along with their cost and your schedule—are tight, and these issues bring power consequences along with them. “Consumer and portable devices are using fewer PCB layers for cost, but the ICs inside them need many voltage levels,” says Dave Kohlmeier, senior product-line director of simulation and analog at Mentor Graphics. These problems don’t apply just to portable products; industrial products have space constraints, too (Figure 1). A modern cell-phone base station has circuitry in a small box on the antenna that used to reside in a 19-in. rack in the building.
Cost is critical in high-volume consumer and automotive products. You can’t afford to sprinkle your PCBs with capacitors that they might not need. To top it off, your design cycles have shrunk to weeks and months instead of years. You can’t take the time to do respins of your PCB to fix and optimize the power and ground planes.
Designing power systems for modern electronics is a daunting challenge. DDR memory operates at 1600 Mbps and will soon run at 2200 Mbps in quad mode. Worse yet, it is a single-ended output, meaning that your power system must deal with sudden changes in power-supply current. Digital gates in the part can all switch at once, a feature that power-integrity engineers characterize as simultaneous-switching noise. Serial communication has difficult power demands. The 802.3ba Ethernet standard calls for 40- and 100-Gbps data rates (Reference 1).
Modern digital chips operate on less than 1V, meaning that even millivolts of noise can cause data-dependent problems. Multiple chips can add statistically and cause power dropout or overvoltage. Your system might work fine for weeks or even months until the digital circuitry all switches at once, causing a system reboot. These power-integrity problems are difficult to troubleshoot. Power-integrity problems on one chip in a system may cause another chip in the system to reboot. “Even a nanosecond of power loss will make your system unreliable,” notes Paul Grohe, an analog applications engineer at National Semiconductor. Minimizing power-supply noise is critical to your design’s reliability, meaning that digital-system engineers must learn analog and even RF-design concepts, according to Steve Pytel, signal-integrity-product manager at Ansys.
Power-system engineers know that power systems must have low impedance (Figure 2), and analog engineers understand that the less noise on the power pin of an analog IC, the better. Unlike digital chips, analog chips have no noise margin. The PSRR (power-supply-rejection-ratio) specification tells you how much of the power-supply noise will seep into the part’s output pin. Digital-system engineers must now deal with the same power-noise issues (see sidebar “Let me talk to someone else”).
The power-delivery network that supplies your chips requires low equivalent inductance—0.01 nH for core voltages and 1 nH for I/O power, according to Brad Brim, product marketing manager at Sigrity. He notes that the power planes couple noise back into your signals. In some cases, a signal routed between two ground planes has 15 mV of noise. When the layout person routed the same signal between the power and the ground planes, it had 45 mV of noise.
Power-integrity tools let you make a deterministic optimization of your design. You cannot use accepted rules of thumb for decoupling to optimize the layout. Software helps you to determine the number, type, and cost of capacitors, says Ansys’ Pytel. These tools also show you the effect of changing the distance between planes. For example, NEC’s PI (power-integrity) Stream helps you meet your target impedance by adding or moving capacitors, changing capacitance values and plane shapes, and altering the distance between power and ground planes, says Yoshi Fukawa, president and founder of TechDream.
“You can use a CAD file for what-if experimentation,” says Mentor’s Kohlmeier. “It is much faster than hardware spins. That is the value of a virtual prototype.” For these reasons, it is important to use simulation software so that you can make important decisions early in the design phase. Capacitor location, capacitor count, and other variables might not affect other departments, but changing the thickness of the board because you moved planes closer to gain interplane capacitance affects the whole design team (Figure 3). Sanmina-SCI has patented modern manufacturing methods that let you design planes with 4-mil-thick dielectrics, increasing interplane distributed capacitance.
Power-integrity simulation is more difficult than many engineers expect because they must account for every capacitor, stitching via, and structure in the power-delivery plane, says Kohlmeier. He points out that stitching vias, which connect two planes, lower the impedance of your power-delivery network and, as such, are just as important as capacitors.
Unlike power integrity, signal integrity usually involves a few traces, and you can measure signal integrity in the time domain with an oscilloscope. Power-integrity simulation yields frequency-domain impedance using the Z11 profile of the impedance from Port 1 to Port 1. To understand the impedance problems of a power plane, you need a VNA (vector network analyzer), which is difficult to use. Simulations are complements, rather than replacements, of measurements, and they provide important information about the performance of the PCB before fabrication. “No matter how fast your simulation software, nothing is faster than a measurement,” says Sigrity’s Brim, who notes, however, that you need a fabricated PCB on which to take that quick measurement.
You must trust that the IC designers have done their job and that the chips you use have no power-integrity problems. “ICs and their bond wires are not that critical in power integrity,” says Ansys’ Pytel, because IC power pins and bond wires are all in parallel (Figure 4). Instead, the layout engineer, who may lack the technical knowledge to avoid power- and signal-integrity problems, determines the power plane’s shape, often causing the problems, according to Steve Kaufer, engineering director for HyperLynx at Mentor Graphics.
Power-integrity software helps you with dc and ac problems, as well as with the fact that the cavities between the power and ground planes are RF waveguides. To deal with the dc problem, you must ensure that the PCB planes can carry the current they must deliver. To deal with the ac problem, you must ensure that the power system can deliver the fast transient currents that modern chips require. Finally, note that the behavior in the waveguide may be nonintuitive. This RF aspect is important in preventing EMI (electromagnetic-interference) problems that will cause your board to fail FCC (Federal Communications Commission) certification. It is important to use simulation if your design has large planes, which can resonate. Adequate software simulation can help your EMI engineer solve problems if your planes spew RF from the interplane cavity. The fix might involve placing capacitors around the edges of the board. Sun Microsystems has patent 6727780, which uses resistors in series with capacitors so RF energy is absorbed at the edge of the board instead of reflected back into the structure.
The digital chips require high currents, which may cause dc-power-delivery problems (Reference 2). FPGAs and other digital chips need many power-supply voltages, so you must divide your power planes to deliver multiple power rails. Digital chips also have hundreds of pins whose fan-out traces require hundreds of vias that wipe out large areas of copper in power and ground planes. You must ensure that the current density in the copper you select for the planes stays below a reasonable value (Figure 5).
High dc current also causes thermal problems. The temperature coefficient of copper is 0.4%/°C, meaning that it adds 10% more resistivity for every 25°C increase in heat. That increase in resistance occurs under heavy loads, when reliability is critical. The increase in resistance also increases temperature, reducing the lifetime of the components on the board.
Once you have enough copper to supply the dc load, look at the ac design of the power plane (Figure 6). Power-integrity simulation lets you examine where the return currents flow in your planes. During operation, a digital chip draws radically different current levels, which change in nanoseconds. Your power system must have low enough ac impedance that the large changes in current, expressed as di/dt (derivative of current over the derivative of time), do not create large power-supply-voltage changes at the chips’ pins. Because di/dt also radiates electromagnetic energy, these excursions can cause EMI problems. As a result, signal integrity, power integrity, and EMI compliance all interrelate. Without simulation, your design may experience via-to-via crosstalk and other issues that might seem inexplicable.
Click here to continue reading: "Power-integrity simulation keeps your planes perfect, part 2."
Click here to continue reading: "Power-integrity simulation keeps your planes perfect, part 2."
You can reach Technical Editor Paul Rako at 1-408-745-1994 and email@example.com.
|For More Information|
|Cadence||Cisco Systems||Computer Simulation
|Giga Hertz Technology||Mentor Graphics||NEC Informatec
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