Design a 100A active load to test power supplies
Ideally, your regulator output is invariant during a load transient. In practice, however, you will encounter some variations, which become problematic if allowable operating-voltage tolerances are exceeded. You can base your active-load circuit on previous designs of wideband loads that operate at lower currents (Reference 1). This approach allows you to design a closed-loop, 500-kHz-bandwidth, 100A active load having linear response.
| Click here to read more of Jim Williams' contributions to EDN.|
Trimming optimizes the dynamic response, determines the loop’s dc baseline idle current, sets the dissipation limit, and controls the gate drive’s stage bias. The dc trims are self-explanatory. The loop-compensation and FET-response ac trims at A1 are subtler. Adjust them for the best compromise between loop stability, edge rate, and pulse purity. You can use A1’s loop-compensation trimming capacitor to set the roll-off for maximum bandwidth and accommodate the phase shift that Q1’s gate capacitance and A3 introduce. The FET-response adjustment partially compensates Q1’s inherent nonlinear-gain characteristic, improving the front and rear pulses’ corner fidelity (see sidebar “Trimming procedure”).
Jim Williams was a staff scientist at Linear Technology Corp, where he specialized in analog-circuit and instrumentation design. He served in similar capacities at National Semiconductor, Arthur D Little, and the Instrumentation Laboratory at the Massachusetts Institute of Technology (Cambridge, MA). He enjoyed sports cars, art, collecting antique scientific instruments, sculpture, and restoring old Tektronix oscilloscopes. A long-time EDN contributor, Williams died in June 2011 after a stroke.
Trimming Figure 5’s circuit is a seven-step procedure that must be performed in order. Out-of-sequence adjustments are permissible if you have adjusted the dissipation-limiter circuitry.
- Set all adjustments to midrange except A1’s feedback capacitor, which should be at full capacity.
- Apply no input. Bias Q1’s drain from a 1V-dc supply. Turn on the power and trim the baseline current for 0.5A through Q1. Monitor this current with an ammeter in Q1’s drain line.
- Turn off the power. Lift Q2’s source lead and let it float, which disables the dissipation-limit circuitry, leaving Q1 vulnerable to damage from inappropriate inputs. Follow the remainder of this step in strict accordance with the instructions. Turn on the power, bias Q1’s drain from a 1V supply, apply a −0.1V-dc input, and monitor Q1’s drain current with an ammeter. Trim the gain adjustment for a 10.5A meter reading. The trimming gain at only 10% of scale mandates the tight trim targets. This limitation is undesirable but less painful than trimming at 100% of scale, which would force astronomical—and brief—dissipation in Q1 and the 1-mΩ shunt resistor. Make this adjustment fairly quickly because Q1 dissipates 10W. Turn off the power and reconnect Q2’s source lead. It is worth mentioning that the primary uncertainty necessitating gain trimming is the sense line’s mechanical placement at the 1-mΩ shunt resistor.
- Turn on the power with no input and with Q1’s drain unbiased. Trim the IQ adjustment for 10 mV at A2’s positive input measured with respect to the −15V rail. Turn off the power.
- Bias and bypass Q1’s drain in accordance with Figure 6. Set the drain’s dc-power supply for 1.5V output and turn on the power. Apply a 1-kHz, −1V-amplitude, 5-μsec-wide pulse. Slowly increase the pulse width until IC1 trips, shutting down circuit output and illuminating the power-limit LED. Tripping should occur at approximately a 12- to 15-μsec pulse width. If it does not, adjust the dissipation-limit potentiometer to bring the trip point within these limits. This step sets the allowable full-amplitude 100A duty cycle at approximately 1.5%.
- Under the same operating conditions as those in Step 5, set the input pulse width at 10 μsec and adjust A1’s capacitive trim for the fastest positive-going edge obtainable at A3’s output without introducing pulse distortion. Pulse clarity should approach that in Figure 7 with somewhat degraded top-front and bottom-rear corner rounding.
- Adjust the FET-response compensation to correct the corner rounding in Step 6. Some interaction may occur with Step 6’s adjustment. Repeat steps 6 and 7 until A3’s output waveform looks like that in Figure 7.
Verifying current measurement
Theoretically, Q1’s source and drain current are equal. Realistically, they can differ due to the effects
of residual inductances and the 28,000-pF gate capacitance. A3’s indicated instantaneous current
could be erroneous if these or other terms come into play. You can verify that the source and the drain currents are equivalent (Figure A). Add a top-side, 1-mΩ shunt and a gain-of-10 differential amplifier to duplicate the circuit’s bottom-side current-sensing section. The results should eliminate concern over Q1’s dynamic-current differences (Figure B). The two 100A pulse outputs are identical in amplitude and shape, promoting confidence in the circuit’s operation.
The pulse-edge rates in the main article are not particularly fast, but high-fidelity response requires some diligence. In particular, the input pulse must be cleanly defined and devoid of parasitics, which
would distort the circuit’s output-pulse shape. A1’s 2.1-MHz input RC (resistance/capacitance) network filters the pulse generator’s preshoot, rise-time, and pulse-transition aberrations, which are
well out of band. These terms are not of concern. Almost all general-purpose pulse generators should perform well.
A potential offender is excessive tailing after transitions. Meaningful dynamic testing requires a rectangular pulse shape, flat on the top and the bottom within 1 to 2%. The circuit’s input band-shaping filter removes the aforementioned high speed-transition-related errors but does not eliminate lengthy tailing in the pulse flats. You should check the pulse generator for this issue with a
well-compensated probe at the circuit input. The oscilloscope should register the desired flat-top- and flat-bottom-waveform characteristics. In making this measurement, if high speed-transition-related events are bothersome, you can move the probe to the band-limiting 300-pF capacitor. This practice is defensible because the waveform at this point determines A1’s input-signal bandwidth.
Some pulse-generator output stages produce a low-level dc offset when their output is nominally at its 0V state. The active-load circuit processes such dc potentials as legitimate signals, resulting in a
dc-load baseline-current shift. The active load’s input scale factor of 1V=100A means that a 10-mV zerostate error produces 1A of dc baseline-current shift. A simple way to check a pulse generator for this error is to place it in external-trigger mode and read its output with a DVM (digital voltmeter). If offset is present, you can account for it by nullifying it with the circuit’s baseline-current trim. You could also use a different pulse generator.
Keep in mind parasitic effects due to probe grounding and instrument interconnection. At pulsed
100A levels, you can easily induce parasitic current into “grounds” and interconnections, distorting displayed waveforms. Use coaxially grounded probes, particularly at A3’s output-current monitor and
preferably anywhere else.
It is also convenient and common practice to externally trigger the oscilloscope from the pulse generator’s trigger output. There is nothing wrong with this practice; in fact, it is a recommended approach for ensuring a stable trigger as you move probes between points. This practice does, however, potentially introduce ground loops due to multiple paths between the pulse generator, the circuit, and the oscilloscope. This condition can falsely cause apparent distortion in displayed waveforms. You can avoid this effect by using a trigger isolator at the oscilloscope’s
external-trigger input. This simple coaxial component typically comprises isolated ground and signal paths, which often couple to a pulse transformer to provide a galvanically isolated trigger event.
Commercial examples include the Deerfield Laboratory 185 and the Hewlett-Packard 11356A. Alternatively, you can construct a trigger isolator in a small
BNC-equipped enclosure (Figure A).