Perfect timing: performing clock division with jitter and phase-noise measurements

Howell Mitchell, Silicon Laboratories - October 20, 2011

When measuring ultra-low-jitter devices and equipment, engineers must constantly ask whether the measurement values are from the DUT (device under test) or from the test equipment. Engineers are also always looking for methods of expanding the reach of the equipment at hand. This article describes some practical ways to handle situations in which clock signals have been divided down from higher-frequency VCOs (voltage-controlled oscillators).

Most modern equipment that measures jitter can be placed into one of two broad categories: time domain or frequency domain. Time-domain equipment typically comes in the form of a high-speed digital oscilloscope with high single-shot sampling bandwidth. Frequency-domain equipment usually comes in the form of a spectrum analyzer, a spectrum analyzer with phase-noise measurement capability, or a phase-noise analyzer. Each of these two categories of equipment has its own set of advantages and disadvantages. However, both measure the same phenomena, albeit with different approaches.

Peak cycle-to-cycle jitter is the maximum difference between consecutive, adjacent clock periods over a fixed number of cycles—typically, 1000 or 10,000. It is used whenever there is a need to limit the size of a sudden jump in frequency. For example, when driving a PLL (phase-locked loop), you may want to limit the size of an instantaneous change in frequency to ensure that downstream PLLs remain in lock (Reference 1 and Figure 1).

Perfect timing: performing clock division with jitter and phase-noise measurements figure 1

The peak-to-peak period jitter is the difference between the largest clock period and the smallest clock period for all clock periods within an observation window—again, typically 1000 or 10,000 cycles (Figure 2). It is a useful specification for guaranteeing the setup-and-hold time of flip-flops in digital systems. “Peak-to-peak” refers to the difference between the smallest and the largest sampled period value during a measurement.

Perfect timing: performing clock division with jitter and phase-noise measurements figure 2

TIE (time-interval-error) jitter, or accumulated jitter—also known as phase jitter—is the actual deviation from the ideal clock period over all clock periods (Figure 3). It includes jitter at all jitter-modulation frequencies and commonly finds use in WAN (wide-area-network) timing applications, such as SONET (synchronous optical network), synchronous Ethernet, and OTN (optical-transport networking).

Perfect timing: performing clock division with jitter and phase-noise measurements figure 3

You can create various types of statistics, such as rms (root-mean-square), peak-to-peak, cycle-to-cycle, period, and TIE jitter, although some are more commonly used than others. Whenever peak-to-peak statistics are used, the number of samples taken must be large enough to produce confidence in the measurement. Such measurements typically include 1000 to 10,000 samples.

Time-domain equipment can directly measure peak-to-peak, cycle-to-cycle, period, and TIE jitter. This measurement approach permits the measurement of jitter for low-frequency clock, or carrier, signals. By employing FFTs (fast Fourier transforms), digital filters, and other techniques to postprocess the data, you can integrate the phase-noise value over a band of frequencies to generate rms-phase-jitter values. Time-domain equipment is better than frequency-domain systems at measuring datadependent jitter, making it useful for high-speed serial links that use SERDES (serializer/deserializer) technology.

Perfect timing: performing clock division with jitter and phase-noise measurements table 1

Frequency-domain equipment cannot directly measure peak-to-peak, cycle-to-cycle, or period jitter; its native ability is to measure the rms power of a signal in a given frequency band. Frequency-domain equipment is also awkward for measuring data-dependent jitter. However, high-quality frequency-domain instruments have lower noise floors than their time-domain counterparts, making frequency-domain units the instruments of choice for ultra-low-phase-noise clock-signal measurements that are free of data-dependent jitter (Table 1).

Because this article focuses on the measurement of low-jitter clock signals, it omits further discussion of time-domain equipment except to mention that you can use various mathematical-estimation and -translation approaches to go from one type of jitter measurement to another. Talkback button

For example, it is possible to use a crest factor and a desired BER (bit-error rate) to go back and forth between peak-to-peak and rms jitter. Another example is using an FFT of time-domain data to provide frequency-domain information and filtering. However, most of these techniques rely on mathematical models, which may be good approximations in most situations but have limitations. As such, you should use them only carefully.

Perfect timing: performing clock division with jitter and phase-noise measurements figure 4

One issue that bears further investigation is the effect of clock, or carrier, frequency on the jitter measurement. It is intuitive that a clock signal divided down by an ideal divider will have the same clock edge jitter at both its input and output (Figure 4). In the figure, the top jittered signal with frequency F_O is divided by two using a perfect divider to produce a clock frequency of F_O/2. Both clock signals have the same jitter, J_O. Note that the jitter energy of the lower clock signal is half that of the higher clock signal because there are half as many edges in a given interval of time.

The intuition that J_O is the same for the two clock signals is for the most part true, despite the fact that the phase noise of a clock signal that is divided by two will be 6 dB lower than the phase noise of the original clock signal. Note that, for division by two, 6 dB=20×log2 (Reference 2).

Perfect timing: performing clock division with jitter and phase-noise measurements figure 5

The following example illustrates the effect of division by powers of two for both phase noise and jitter. These measurements employ a Silicon Laboratories Si5324 PLL device (Figure 5). Note that the high-speed VCO resynchronizes the output clock, regardless of the final output frequency, meaning that the edge shape and placement should be the same for all possible divider values. The only difference should be that fewer clock edges occur during a given time interval. Although some retiming noise remains, the noise is the same for all of the divisor values (Figure 6).

Perfect timing: performing clock division with jitter and phase-noise measurements figure 6

The six curves in the figure are essentially the same but with a vertical separation of 6 dBc/Hz. The 6-dB separation is relatively constant over all offset frequencies and divisor values, with one or two exceptions. On the right side of the plot, in which the offset from the clock, or carrier, is at its largest, the relative vertical offsets between the curves are compressed. The compression increases as the clock frequency decreases. This compression becomes more pronounced as the clock frequency and the phase-noise-curve values decrease. The compression occurs because the noise floor of the Agilent Technologies model E5052B signal-source analyzer nears the value of the phase noise, or jitter generation, of the Si5324 IC. The noise floor is an issue only because of the combined effect of the ultra-low jitter of the Si5324 and the low carrier frequency. Table 2 lists the corresponding jitter values for each of the six plots with the jitter integrated from 100 Hz to 20 MHz and all jitter values in femtoseconds rms.

Perfect timing: performing clock division with jitter and phase-noise measurements table 2

Notice that the jitter increases slightly as the output frequency decreases—evidence that the output jitter is relatively constant despite the fact that 6 dB separates the phase-noise curves from one another. The rate at which the jitter increases becomes more pronounced at the lowest output frequencies. Let’s examine the two sources of the increased rms-phase-noise values: instrument noise floor and aliasing.

Noise floor, phase noise

The instrument’s noise floor can become the limiting factor of a measurement of phase noise of very-low-jitter clocks at low clock frequencies. At some point, you are measuring your equipment, not the DUT. Even though the phase-noise curves become monotonically smaller as the clock frequency decreases, the rms edge jitter remains almost constant because the phase-noise integration uses the clock period to scale the rms-jitter values.

Perfect timing: performing clock division with jitter and phase-noise measurements figure 7

To illustrate how this scenario occurs, consider the process of phase-noise integration to produce an rms-jitter value. Most modern phase-noise equipment produces a file that has two columns—typically, a CSV (comma-separated-value) file. One of the two columns lists the frequency offset from the clock, or carrier, frequency in hertz. The other column lists the phase-noise values at that offset frequency in decibels referenced to the carrier per hertz. Thus, the columns contain data-point pairs that describe the phase noise at a given offset from the clock frequency. Integration involves summing the area under the curve for all of the frequency-offset points after converting the decibels-referenced-to-the-carrier-per-hertz values to linear values using the following equation: Linear values=10^(dBc/Hz)/10.

Perfect timing: performing clock division with jitter and phase-noise measurements figure 8

The equation for the area of a trapezoid in Figure 7 is used to find the area described by two adjacent data-point pairs. You find the area under the curve by summing the area of all of the trapezoids. The final rms-jitter value is determined by scaling the result by two factors: The value

comes from the fact that the data was taken as one sideband; however, the rms jitter is assumed to be dual sideband. It is usually safe to assume that the two sidebands of the phase noise are symmetric about the clock frequency. In this case, it is even safer because a limiting amp suppresses AM (amplitude modulation) and passes FM (frequency modulation) to ensure symmetric sidebands (Figure 8).

The other scaling factor converts the area sum so that it is no longer in UIs (unit intervals) but in units of time. This factor keeps the rms edge jitter’s values relatively constant, whereas the phase-noise values change. The equation for rms jitter is expressed as follows:

Perfect timing: performing clock division with jitter and phase-noise measurements equation

where F_C is the clock frequency, N_i is the phase noise in decibels referenced to the carrier per hertz for the ith entry, and F_i is the offset frequency for the ith entry.

Aliasing

Aliasing is another cause of increasing rms-jitter values with decreasing clock frequency. For every division of two, the upper half of a phase-noise plot aliases down into the new lower-clock-frequency phase plot. Because phase noise is usually higher close to the clock or carrier frequency and drops off as the offset from the clock frequency increases, relatively little phase noise aliases down. However, when dividing by large numbers, the effect becomes cumulative and significant. For example, the difference between the 1280- and the 640-MHz curves in Figure 1 is a constant 6 dB across the entire plot. As a result, you would expect that the increased rms-jitter values for the two curves in Table 2 are due entirely to aliasing and not to the instrument’s noise floor.

Perfect timing: performing clock division with jitter and phase-noise measurements figure 9

Perfect timing: performing clock division with jitter and phase-noise measurements figure 10

The spectra and phase-noise plots in Figures 9 through 13 illustrate aliasing. The signals in these examples use AM to illustrate aliasing and are not what would be expected in a typical application. Figures 9 and 10 show the spectra and phase-noise plots for the 3-GHz signal. The plots show symmetrical spurs at frequencies of 400 MHz above and below the 3-GHz clock frequency. When the spectrum shows two equal sidebands, the phase-noise plot of the same signal combines their effect into one spur 400 MHz from the 3-GHz carrier. A divide-by-four circuit then divides down the 3-GHz signal to produce 750 MHz.

Perfect timing: performing clock division with jitter and phase-noise measurements figure 11

Perfect timing: performing clock division with jitter and phase-noise measurements figure 12

Figures 11 and 12 show the spectra and phase-noise plots of the 750-MHz signal from the divide-by-four circuit. As a result of the division by four, the spurs at 2.6 and 3.4 GHz alias down to a sideband spur at 350 MHz. Note that 350 MHz is a frequency value that is the same 400 MHz from the 750-MHz carrier as 2.6 GHz is from the 3-GHz carrier. To further illustrate the aliasing, the 750-MHz signal is again divided down to 375 MHz. The 25-MHz spur in Figure 13 is an alias of the spur at 350 MHz in Figure 11; that is, 25 MHz=375 MHz−350 MHz.

Perfect timing: performing clock division with jitter and phase-noise measurements figure 13

As you can see, the instrumentation’s noise floor can become a limiting factor when measuring low-jitter clocks with low-frequency values. When a higher-frequency clock divides down the clock being measured, you can lower the value of the divider so that the measurement takes place at a higher frequency. However, this commonly used technique removes the jitter contribution from higher-frequency jitter components that would have been aliased down by the division. Although the resulting rms-jitter values may be artificially lower, this approach is acceptable in applications in which the phase noise that is far off of the corner is relatively small. When measuring low-frequency clocks with appropriately high amounts of jitter, use time-domain equipment because the measurement can be made at the actual desired output frequency, no matter how low the clock frequency may be.

Acknowledgment
This article originally appeared on EDN’s sister site, Test & Measurement Designline.

References

Li, Mike Peng, Jitter, Noise, and Signal Integrity at High-Speed, Prentice Hall, 2008, ISBN: 0-13-242961-6.
Gardner, Floyd M, Phaselock Techniques, Third Edition, John Wiley & Sons, 2005, 0-471-43063-3.

Author's biography

Howell Mitchell is a staff applications engineer at Silicon Laboratories, where he is responsible for product support for a family of jitter-attenuating PLL-based timing devices. Before joining Silicon Labs, he was a principal engineer at MagiQ Technologies, where he worked in quantum-key distribution. Mitchell holds five patents in phase modulation and quantum-key distribution. He received a bachelor’s degree in physics from Bucknell University (Lewisburg, PA) and a master’s degree in engineering from Northeastern University (Boston).