Circuit simultaneously delivers square and square root of two input voltages

Marián Štofka, Slovak University of Technology, Bratislava, Slovakia - March 1, 2012

This Design Idea requires inputs from the circuit in a previous Design Idea (Reference 1). IC₁ and IC₃ are ADG5213 quad switches with individual logic-level control inputs (Figure 1 and Reference 2). With a high input, switches S₂ and S₃ are open, and switches S₁ and S₄ are closed. The switches toggle to opposite states with their control inputs low. The circuit is in the idle pretriggered condition. During the initial idle condition before a clock rising-edge trigger, Q is high and, through IC₈, holds switches S₂ and S₃ of IC₁ in the open position.

Circuit simultaneously delivers square and square root of two input voltages figure 1

is low, and, through IC₇’s Reset high closes IC₁’s S₁ and S₄, discharging C_T2 and C_T4 and zeroing the input voltage to unity-gain amplifiers IC_2D and IC_2C.

low also sets Track 2 low through IC₆ and holds IC₃’s S₁ and S₄ in the open position. The circuit retains any sampled voltages from a previous operation in sample-and-hold capacitors C_S1 and C_S2; these voltages appear at V_OUTX and V_OUTY through unity-gain amplifiers IC_2A and IC_2B.

Signals V_OUTL and V_OUTQ from the linear and quadratic pulse generator are at 0V during idle, holding comparator outputs IC₄ and IC₅ low. A rising trigger edge at the clock signal begins the ramp generation of V_OUTL and V_OUTQ. The Q and IC₈ outputs fall low, closing IC₁’s S₂ and S₃ and ensuring that Track 2 remains low.

rises and forces Reset low through IC₇, opening S₁ and S₄ of IC₁ and allowing C_T2 to follow the rising V_OUTQ and C_T4 to follow the rising V_OUTL.

When linear ramp V_OUTL rises to analog input V_X, IC₄’s output rises and, through IC₈, Track 1L opens S₂ of IC₁ and allows C_T2 to hold the present level of V_OUTQ. In a similar manner, when quadratic ramp V_OUTQ rises to analog input V_Y, IC₅’s output rises and, through IC₈, Track 1Q opens IC₁’s S₃ and allows C_T4 to hold V_OUTL’s present level. The pulse generator terminates when the ramps reach 5V. The ramps then fall back to 0V, Q returns high, and

returns low.

The fall of

triggers IC₇ to produce a 50-μsec delayed rise on Reset, which R_D2 and C_D2 time to occur after Track 2 has returned low and the sampled voltages are safely captured on C_S1 and C_S2. Reset’s high state closes IC₁’s S₁ and S₄, discharging C_T2 and C_T4 in preparation for the next trigger. V_OUTX is the squared voltage of input V_X, and V_OUTY is the square root of the voltage of input V_Y.

Operation of the circuit is illustrated in Figure 1. For the sake of simplicity, both analog input voltages V_X and V_Y have a value of (3/5)V_PEAK; V_PEAK represents here a full-scale of both input voltages. The V_X, which is compared by IC₄ comparator with the linear sawtooth pulse V_OUTL produces therefore a pulse width of

. Subsequently, the trailing edge of the latter pulse width stops tracking of the quadratic sawtooth voltage V_OUTQ at the level of

Circuit simultaneously delivers square and square root of two input voltages figure 2

Contrarily, V_Y is compared in IC₅ comparator with the quadratic V_OUTQ reference pulse and the resulting pulse width at output of COMP_Q has a value of

. Trailing edge of this pulse stops tracking of linear V_OUTL time-base at the level of

. If you normalize both output voltages by V_PEAK, you get numbers of

and

, and these correspond to square and square root of the input of "3/5".

Circuit simultaneously delivers square and square root of two input voltages figure 3

Note that the described circuit is flexible with its further possibilities to create other mathematical functions. If you need fourth power of input voltage,

, you connect output of X channel to input of Y channel; while you slightly rearrange the COMP_Q comparator IC₅ by disconnecting its positive input and connecting it to positive input of the COMP_L comparator IC₄. At output of Y channel you get the desired function of

. In other words, you made this way a cascade of two identical squaring channels.

Similarly you can connect a cascade of two identical square-rooting channels, which offers you fourth-root function,