Product How-To: Passive filter options achieve very high SNR, SFDR in a low-power 16-bit ADC interface (Part 1)
Michael Steffes and Jian Wang, Intersil Corp. - May 15, 2012
Emerging 14 and 16 bit high frequency ADCs are offering > 75 dBc SNR for the ADC alone. Along with this comes SFDR performance pushing above 90 dBc and even 100 dBc levels over some frequency span. The higher SFDR numbers come at a big increase in quiescent power. Figure 1 shows a comparison of performance vs. power dissipation for several recent 16 bit high speed (>=125 MSPS) ADCs.
Figure 1. Best effort data sheet extraction at 65 MSPS and 20 MHz for several 16 bit ADCs (no-dither)
From the chart above, the ISLA216P251 offers one of the lowest power options in the >100 MSPS space with exceptional SNR and SFDR performance. Designed to support a maximum 250 MSPS operation, some fixed digital overhead power prevents it from scaling down in power at lower clock rates quite as far as some devices designed specifically for only 125 MSPS or lower clock rates. While the designs here will be looking at total noise in the FFT, a higher clock rate part like the ISLA216P25 holds open the option of oversampling to achieve extremely low narrowband noise using processing gain.
Using a combined amplifier + ADC evaluation board2, design options at lower clock rates and analog input bands will be explored. This particular board provides an AC coupled single ended 50Ω input termination, converts to differential through an input transformer, then feeds into a Fully Differential Amplifier (FDA) gain stage configured as a differential I/O stage using the ISL55210.3 A simplified signal path up to the amplifier outputs is shown in Figure 2.
Figure 2. Single-to-differential, AC-coupled, improved noise and distortion input interface to ADC.
This configuration provides a number of subtle advantages towards improving the output dynamic range for a given gain target. The transformer combines with this 115 mW, 4 GHz, ISL55210 FDA to give the following:
- The input signal current in the transformer primary becomes a “single” signal current in the transformer secondary driving into the sum of the two Rg resistors to the differential virtual ground of the FDA inverting inputs. It is important to NOT use any secondary center tap on the transformer to avoid any imbalance issue in the two halves of the secondary.
- The termination impedance is totally set by the 2*Rg. No signal current is wasted into shunt termination paths which gives a noise figure advantage.
- If the Rg resistor sets the input termination, then Rf is simply adjusted to give the amplifier gain. It is useful, therefore, that the FDA be a Voltage Feedback Amplifier (VFA) like the ISL55210 to have more flexibility in the Rf value. Current feedback based FDA’s can provide exceptional slew rate but will not get to the lowest noise nor be as useful in this configuration.
- For VFA based designs, this configuration gives more signal gain than noise gain. The total signal gain is going to be n*(Rf/Rg). However, if the source impedance is in fact equal to (2*Rg/n2), and we consider the total impedance looking back towards the source from the inverting summing junctions, that source impedance will make the impedance on each leg look like 2Rg. The noise gain then becomes 1+ (Rf/ (2*Rg). This is a slight, but very useful, effect in reducing the output noise produced by the amplifiers input voltage noise and the Rg resistor noise terms.
- This reduction in noise gain (while still giving a higher signal gain) also directly increases the loop gain for VFA based design. All other things being equal, any increase in loop gain will decrease the distortion terms directly.
For instance, if we configure the board to use a 1:2 turns ratio transformer from a 50Ω source, the Rg resistors will each be 100Ω and, for a total gain of 12 V/V, the Rf resistors become 604Ω. Then, while we are getting a signal gain of 12 V/V design, the “Noise Gain” for the FDA will be only 4 V/V. This will obviously also provide a much broader bandwidth for any given “Gain Bandwidth Product” in a VFA based design. For instance, the 4 GHz Gain Bandwidth Product of the ISL55210 will then give about 1 GHz closed loop bandwidth for this example and the Vi to Vo bandwidth will almost certainly be set by the input transformer bandwidth.
This extremely broad amplifier bandwidth implies significant loop gain at lower frequencies, which is good for distortion, but also an immense spot noise bandwidth at the output pins. It is precisely this conundrum that creates the need for an inter-stage filter. Having >1 GHz amplifier bandwidth is going to deliver very low distortion at the <20 MHz input frequencies intended here, but at the same time, a very wideband noise source. More detail on the nuances and analysis of this interface approach can be found in Ref. 4.