Analog: back to the future, part one
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Examining history provides an eye-opening education into our predecessors’ successes and failures and may provide lessons on what to avoid and what to emulate in our lives. This fact holds true not only in daily life but also in analog-IC and analog-circuit design. Innovative developers and developments were the foundations that led to 21st-century analog products that we now use in design. This article delves into early precision-op-amp development from National Semiconductor, Texas Instruments, and Linear Technology. Future installments will focus on Burr-Brown, Analog Devices, Microchip, and Maxim and on pioneers in analog technology.
|At A Glance|
- National Semiconductor designers provide a snapshot of the challenges of IC design from 30 to 40 years ago and how those experiences brought about today’s ICs.
- Designers developed so-called kludge boxes to verify the performance of designs and sometimes later used them in production-test equipment.
- Designers used simulation tools for validation, but they had to first perform manual calculations, and breadboarding was standard practice until the mid-1980s.
- Bob Dobkin, Linear Technology’s co-founder, vice president of engineering, and chief technology officer, spent his early design days at National Semiconductor, where his creativity was evident in moving early op amps beyond the 1-MHz-bandwidth barrier.
By experiencing and learning from their growing pains along the course of IC development, a few designers stand out. Several of these designers were originally with National Semiconductor but are now part of Texas Instruments, and they are guiding chip-design engineers along a new path of success for the next level of ICs that circuit designers so desperately need in today’s demanding market. According to Dennis Monticelli, TI fellow, the story of computers is also the story of IC development; you can’t separate them. His co-worker, Chief Technology Officer Erroll Dietz, remembers the early days of analog ICs as the “Wild West of electronics.” Using design rules that they made up as they went along, these designers worked from transistor-kit parts, used copper-clad breadboards with sockets as design tools, and employed discrete resistors and capacitors (Figure 1).
“Kit parts were transistors manufactured in the linear IC-fab lines bonded up in metal can packages,” says Mike Maida, a distinguished member of the technical staff at TI. “Design rules [used] spacing to adhere to in IC layouts—for example, base to isolation, emitter inside base, [and the like]. Designers sometimes figured out their own [design rules] for special situations, such as reduced voltages, although the fab engineers had to sign off on them. We had little mylar ‘rulers’ to measure spacings on the IC composite drawings.”
The designers performed simulations using Level 2 Spice, which used an enhanced Grove equation, the most common MOS equation in all simulators. HKJ Ihantola and JL Moll in 1964 developed the equation (Reference 1). A discontinuity in transconductance at the time made life difficult for designers. Designs operating at frequencies higher than a few megahertz were difficult to breadboard, for example. “Simulation is a late-’70s thing,” says Maida. “No one simulated linear ICs [then].”
“There was a large discontinuity in the Level 2 MOS model for the region between strong inversion and weak inversion,” says Don Archer, also a distinguished member of the technical staff at TI. “When operating in the quasi-subthreshold region, model discontinuity was a major problem for convergence, and, when we started, there was no modeling group. We measured kit parts and came up with our own model parameters.”
The designers also lacked the ability to capture schematics; they had to manually type the netlist, including emitter, base, and collector values, and manually generate a schematic to check the accuracy of those values. They then added the simulation-node numbers to the hand-drawn schematic. The lines in the netlist might read, for example, Q1 8 7 4 0 NPN1, which would mean that Q1 is device type NPN1, with a collector node of eight, a base node of seven, an emitter node of four, and a substrate node of zero. They had to type a similar line for every transistor, resistor, and capacitor.
“To look at waveforms, we had to use plot and print [commands] to specify nodes to be printed or plotted,” says Farhood Moraveji, technical director at TI. “For more complex circuits with hierarchy, we had to use [a subcircuit command]. Back-end tools didn’t exist or were primitive. DRCs [design-rule checks] and LVS [layout-versus-schematic] checks were not automatic, and peers used to perform independent, manual LVS checks to verify that the circuit and the layout matched.”
Layout tools included a “beer check,” during which the designers placed circuit plots onto a light table. “You would invite your peers to the beer check for your IC layout,” says Archer. “You would buy them a beer for every mistake they found. We later got a more staid design manager, who insisted we call them layout checks instead of beer checks.”