Understand the digital-output options for high-speed ADCs
Jessica MacNeil -June 06, 2012
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With a multitude of ADC choices available for designers, they must consider what type of digital-data outputs to use: CMOS (complementary metal-oxide semiconductor), LVDS (low-voltage differential signaling), or CML (current-mode logic). Each of the digital-output types used in ADCs has advantages and disadvantages that designers should consider for their applications. These factors depend on the sampling rate and the resolution of the ADC, the output data rates, and the power requirements of the system design, among other factors.
CMOS digital outputs are common in ADCs with sample rates lower than 200M samples/sec. A typical CMOS driver comprises one NMOS transistor and one PMOS transistor, which connect between the drain-to-drain, or power-supply, voltage, VDD, and ground (Figure 1a). This structure results in an inversion in the output. Alternatively, you can use a back-to-back structure to avoid the inversion in the output (Figure 1b).
The CMOS output driver has a high-impedance input and a low-impedance output. At the input to the driver, the impedance of the gates of the two CMOS transistors is quite high because the gate oxide isolates the gate from any conducting material. The impedances at the input can range from kilohms to megohms.
At the driver’s output, the drain current, ID, which is typically small, governs the impedance. In this case, the impedance is usually less than a few hundred ohms. The voltage levels for CMOS swing from approximately the power-supply voltage to ground and can therefore be large, depending on the power-supply voltage. Because the input impedance is high and the output impedance is relatively low, one CMOS output can typically drive multiple CMOS inputs.
CMOS outputs also have low static current. Significant current flow occurs only during a switching event on the CMOS driver. When the driver is in either a low state—that is, pulled to ground—or a high state—that is, pulled to the power-supply voltage—little current flows through the driver. However, when the driver is switching from a low state to a high state or from a high state to a low state, a momentary low-resistance path occurs from the power-supply voltage to ground. This transient current is one of the main reasons that designers typically use other technologies for output drivers in ADCs with sampling rates higher than 200M samples/sec.
Another reason is that each bit of the converter requires a CMOS driver. A 14-bit ADC requires 14 CMOS output drivers. This constraint requires the use of more than one converter in a package; the use of as many as eight converters in a package is common, compounding the problem of multiple drivers. For example, using CMOS technology could require as many as 112 output pins for just the data outputs. This arrangement would not only be prohibitive from a packaging standpoint but also would consume more power and increase the complexity of the PCB layout. To combat these issues, manufacturers introduced an interface using LVDS.
LVDS offers some advantages over CMOS technology, including the facts that it operates with a signal of only approximately 350 mV and that it is differential rather than single-ended. The lower voltage swing has faster switching and reduces EMI concerns. Because LVDS technology is differential, it also has common-mode rejection, meaning that noise that couples to the signals tends to be common to both signal paths, and the differential receiver cancels out most of it.
You must more tightly control the impedances in LVDS, and the load resistance must be approximately 100Ω. Designers typically achieve this resistance by using a parallel-termination resistor at the LVDS receiver. You must also route LVDS signals using controlled-impedance transmission lines. Single-ended designs require 50Ω impedance, whereas differential designs maintain impedance at 100Ω (Figure 2).
As the LVDS-output-driver topology shows, the circuit’s operation results in a fixed dc-load current on the output supplies, avoiding the current spikes seen in a typical CMOS output driver when the output-logic state changes. The nominal current source/sink in the circuit is 3.5 mA, which results in a typical output voltage swing of 350 mV with a 100Ω termination resistor. The common-mode level of the circuit is typically 1.2V, which is compatible with 3.3, 2.5, and 1.8V supply voltages.
The most common standard for LVDS is the ANSI/TIA/EIA-644 specification, “Electrical Characteristics of Low Voltage Differential Signaling Interface Circuits.” Another is the IEEE standard for LVDS for the SCI (scalable coherent interface). LVDS requires careful attention to the physical layout of the routing of the signals but offers many advantages for converters that sample at 200M samples/sec or more. The constant current of the LVDS driver allows you to drive many outputs without the large amount of current draw that CMOS would require. You can also operate LVDS in DDR mode, which routes 2 data bits through the same LVDS-output driver, requiring half the number of pins that CMOS requires.
LVDS also reduces power consumption for the same number of data outputs. However, as converter resolution increases, PCB layouts have a more difficult task of handling the many data outputs that an LVDS interface requires. The ADCs’ sample rates eventually push the interface’s required data rates beyond the capabilities of LVDS.
Next: CML drivers
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