Survival guide to high-speed A/D converter digital outputs

With a multitude of analog-to-digital converters (ADCs) available for designers to choose from, an important parameter to consider in the selection process is the type of digital data outputs included. Currently, the three most common types of digital outputs utilized by high speed converters are complementary metal oxide semiconductor (CMOS), low-voltage differential signaling (LVDS), and current-mode logic (CML).

Each of the digital-output types used in ADCs has advantages and disadvantages that designers should consider in their particular application. These factors depend on the sampling rate and resolution of the ADC, the output data rates, the power requirements of the system design, and others.

In this article, the electrical specifications of each type of output will be discussed, along with what makes each type suited for its particular application. These different types of outputs will be compared in terms of physical implementation, efficiency, and the applications best suited for each type.

CMOS digital output drivers

In ADCs with sample rates of less than 200 Msps (megasamples/sec), it is common to find that the digital outputs are CMOS. A typical CMOS driver consists of two transistors—one NMOS and one PMOS—connected between the power supply (V_DD) and ground as shown in Figure 1a. This structure results in an inversion in the output, so as an alternative, the back-to-back structure in Figure 1b can be used, to avoid the inversion in the output.

The input of the CMOS output driver is high impedance while the output is low impedance. At the input to the driver, the impedance of the gates of the two CMOS transistors is quite high, since the gate is isolated from any conducting material by the gate oxide. The impedances at the input can range from kΩ to MΩ.

At the output of the driver, the impedance is governed by the drain current, I_D, which is typically small. In this case, the impedance is usually less than a few hundred ohms. The voltage levels for CMOS swing from approximately V_DD to ground and can therefore be quite large depending on the magnitude of V_DD.

Figure 1: Typical CMOS digital output driver:

left) inverted output; right) non-inverted output

Since the input impedance is high and the output impedance is relatively low, an advantage that CMOS has is that one output can typically drive multiple CMOS inputs.

Another advantage to CMOS is the low static current. The only instance where there is significant current flow is during a switching event on the CMOS driver. When the driver is in either a low state (pulled to ground), or in a high state (pulled to V_DD), there is little current flow through the driver. However, when the driver is switching from a low state to a high state or from a high state to a low state, there is momentarily a low-resistance path from V_DD to ground. This transient current is one of the main reasons why other technologies are used for output drivers when converter speeds go beyond 200 MSPS.

Another reason is that a CMOS driver is required for each bit of the converter. If a converter has 14 bits, there are 14 CMOS output drivers required to transmit each of those bits. Commonly, more than one converter is placed in a given package and up to eight converters in a single package are common.

When using CMOS technology, this could mean that there would be up to 112 output pins required just for the data outputs. Not only would this be prohibitive from a packaging standpoint, but it would also have high power consumption and increase the complexity of board layout. To combat these issues, an interface using LVDS was introduced.

LVDS digital output drivers

LVDS offers some nice advantages over CMOS technology. It operates with a low-voltage signal, approximately 350 mV, and is differential rather than single-ended. The lower voltage swing has a faster switching time and reduces EMI concerns.

By virtue of being differential, there is also the benefit of common-mode rejection. This means that noise coupled to the signals tends to be common to both signal paths and is mostly cancelled out by the differential receiver.

The impedances in LVDS need to be more tightly controlled. In LVDS, the load resistance needs to be approximately 100 Ω and is usually achieved by a parallel termination resistor at the LVDS receiver. In addition, the LVDS signals need to be routed using controlled-impedance transmission lines. The singled-ended impedance required is 50 Ω while the differential impedance is maintained at 100 Ω. Figure 2 shows the typical LVDS output driver.

Figure 2: Typical LVDS output driver

As shown by the topology of the LVDS output driver in Figure 2, the circuit operation results in a fixed DC-load current on the output supplies. This avoids current spikes that would be seen in a typical CMOS output driver when the output logic state transitions. The nominal current source/sink in the circuit is set to 3.5 mA, which results in a typical output voltage swing of 350 mV with a 100 Ω termination resistor. The common mode level of the circuit is typically set to 1.2 V, which is compatible with 3.3 V, 2.5V, and 1.8 V supply voltages.

There are two standards that have been written to define the LVDS interface. The most commonly used the ANSI/TIA/EIA-644 specification entitled “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.”  The other is the IEEE standard 1596.3 entitled “IEEE Standard for Low Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI).”

LVDS does require that more careful attention be paid to the physical layout of the routing of the signals, but offers many advantages for converters when sampling at speeds of 200 MSPS or greater. The constant current of the LVDS driver allows for many outputs to be driven without the large amount of current draw that CMOS would require.

In addition, it is possible to operate LVDS in a double-data rate (DDR) mode, where two data bits can be routed through the same LVDS output driver. This reduces the number of pins required by one half, compared to CMOS.

Also, the amount of power consumed for the same number of data outputs is reduced. LVDS does offer numerous benefits over CMOS for the data outputs of converters, but it eventually has its limitations as CMOS does. As converter resolution increases, the number of data outputs required by an LVDS interface becomes more difficult to manage for PCB layouts. Furthermore, the sample rates of converters eventually push the required data rates of the interface beyond the capabilities of LVDS.