# Product How-To: Passive filter options achieve very high SNR, SFDR in a low-power 16-bit ADC interface (part 2)

*(Part 1 of this article looked at combined SNR and SFDR in last stage interfaces to high performance
ADCs)*

**Comparing performance between two possible inter-stage filters. **

The inter-stage filter design will need to include the ADC input R and C. Normally, combining those with some external elements will tighten the distribution and allow some tuning in the final response. One of the other goals in the filter would be to reduce the insertion loss but that usually conflicts with holding the differential load appearing at the amplifier output pins higher.

While most amplifiers can certainly handle a varying load to low values, the distortion terms will come up quickly if the load gets too low. The first filter was intended to be flat through 20 MHz then roll off from there. Figure 3 shows a simplified schematic of the Chebychev design described earlier implemented in a free down-loadable Spice simulator (ref. 7).

Shown also are the element tolerances for the design. The shunt capacitors can be 5% while 2% on the inductors seems adequate for repeatable filter response with minimal Differential Mode ßàCommon Mode conversion. Using the Monte Carlo feature of ref. 7, showed about 0.6dB gain variation in band for these tolerances.

**Figure 3. 0.2 dB ripple, AC coupled 25 MHz 3 ^{rd} order Chebychev filter**

The single ended version of the filter design starts by setting the final filter resistance. Here that is the parallel combination of the internal 150 Ω (1/2 of the 300 Ω differential load) and the 975 Ω Vcm bias resistor (130Ω parallel load). Then, to get a low insertion loss, the input resistor to the filter is specified at 40Ω. Note the AC1 source above would be the FDA output signal while V4 would be the FDA common mode voltage. That 1.2Vcm is level shifted to the ADC input Vcm (V2 above at 0.94V) through the 4.7uF blocking caps.

The board version of this simplified circuit also included an adjustment in the V2 voltage for the ADC clock rate dependent common mode current and the 975Ω elements were split into a passive differential to single ended sense path for response measurement (ref. 8). The inductor was also snapped to a standard value and the caps converted to differential by cutting the single ended design values in ½ and, for Cp1 above, reducing its value by the estimated ADC input capacitance.

Figure 4 shows the expected response in simulation – giving a nominal -2 dB insertion loss and a low** **ripple, fast cutoff, 3^{rd} order Chebychev shape. This looks like a very desirable response shape for controlling the broadband noise but will have some phase ripple towards band-edge.

**Figure 4. Simulated response shape for the 0.2 dB ripple, 25Mhz F-3dB Chebychev. **

Figure 5 shows the expected differential input impedance of the filter –
the load to the FDA.

**Figure 5. Differential Input impedance (ohms) for filter of Figure 3. **

This is clearly showing one of the key issues in these designs. While the load is >200 ohm below 5 MHz, in that 10 MHz to 20 MHz region it is actually a pretty heavy load to the FDA for distortion purposes. Countering that issue is the fact that, for single tone HD terms, the filter will be attenuating those HD terms at frequencies approaching band-edge.

Putting all of this together for test purposes gave the board of Figure 6 (ref. 2)

**Figure 6. Physical test board using amplifier + 16 bit ADC**

This board is getting an input 10 MHz at 200 mVp-p on the right side, going through a step up then a common mode choke transformer into the ISL55210 and then the inter-stage differential filter and on into the ADC (right to left here). The clock is coming in at the top and with the obvious cap patched in here, one might be expected a Rev. B version to be the coming along – and that would be a very astute and correct inference

Testing with a very clean (low jitter, very low harmonic distortion , and narrow band-pass filtered) 10 MHz signal delivered to the amplifier + filter at only 200 mVp-p and then into the ISLA216P25 clocking at 65.5 MSPS gives the FFT of Figure 7 (ref. 9)

**Figure 7. 10 MHz FFT Using the 25 MHz Chebychev filter. **

Since these SNR’s and HD terms are so low, several critical considerations need attention in order to achieve the results shown.

Here, we are using windowing and a large FFT length (Blackman Harris 4-term and 2^{19} samples)

Beyond that, we are running a continuous 10 sweep averaging.

The ISLA216P25 is running 2-14 bit cores and calibrating to get 16 bit performance. Here that calibration is running in background and is continuous.

The input level was slightly reduced to hit-2.7 dBFS (for this 2 Vp-p maximum input ADC, that will be 1.47Vp-p at the ADC inputs and, considering the -2 dB filter insertion loss, 1.85Vp-p at the FDA output pins).

While the clock was low phase noise and Band-pass filtered, it also proved critically important to deliver a large amplitude clock signal to get the best results. 10 dBm (2Vp-p) was used here.

Going off 65 MHz to 65.5 MHz spread the spurious out a bit more showing the overall low levels of each.

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