Why JESD204B may solve a lot of your system design headaches
Thomas Neu - November 19, 2012
Recently a new digital interface standard (JESD204B) used for communication between data converters and processors, FPGAs and ASICs has been ratified and its industry-wide adoption is quickly picking up speed. It promises to overcome many limitations posed by traditional interfaces like CMOS or LVDS, such as synchronization across multiple channels or board design complexity.
In recent years an evolution has been unfolding in digital interconnection of high speed (> 10 MSPS) data converters. The goal is to minimize board space and improve reliability, all the while data converter sampling rates increase.
The first industry standard interface introduced in the late 1990s for high speed data converters was parallel LVCMOS. It uses one output pin-per-bit of resolution (a 16-bit ADC uses 17 pins with 16x data and one clock output) and offers very low power consumption. However, analog-to-digital converters (ADCs) are sensitive to the ground noise generated by the transitioning of the single-ended LVCMOS outputs. The rise and fall times of the LVCMOS interface limits the maximum data rate to about 150 MSPS.
The use of the LVDS interface standard for high speed data converter interfaces emerged in 2004. Its differential, constant current architecture is an easy way to eliminate the LVCMOS interface power supply bounce problem. Additionally, because of its differential nature, it is more immune to external noise and crosstalk. LVDS interfaces support data rates in excess of 1 Gbps, but require two pins per output bit, which doubles the interface pin-count and increases the size of the device packages. For instance, a 16-bit ADC with standard LVDS interface requires 34 pins.
To reduce the pin count, the double data rate (DDR) LVDS interface gained popularity starting in 2005. One differential pair transmits two bits of data at twice the converter sampling rate. In a 16-bit ADC, for example, the 8 MSBs can be transmitted on rising edge of the output clock and the 8 LSBs on the falling edge. This reduces the number of output data pins by 50 percent compared to standard LVDS, but doubles the LVDS speed. This requires more care on matching the line length to maximize valid setup and hold time windows.
The next step in the interface evolution was driven by the need to interface a high density of converter channels, for applications such as portable ultrasound equipment with 64+ channels (late 2005). A drastic reduction of IO pins was needed and the serial LVDS (SLVDS) was created. With SLVDS, a 16-bit ADC uses one or two differential LVDS pairs to transmit serialized data at 16x or 8x the ADC sample rate.
In addition to the serialized data outputs for all converters, a bit clock and frame clock are transmitted and shared by the outputs of all converters. For instance, a quad-16-bit 125 Msps ADC uses only 10 differential pairs toggling at 1Gbps. However, the practical max data rate for LVDS of ~ 1Gbps limits the maximum ADC sampling rate to about 125 Msps for 2 output pairs/ADC and 62.5 Msps for 1 output pair/ADC.
Table 1. Digital interface pin requirements for dual 16-bit ADC.