Design Con 2015

Optimizing clock trees to meet performance and system cost targets

-November 19, 2012

Hardware design in high-performance applications such as communications systems, wireless infrastructure, servers, broadcast video, and test and measurement equipment is becoming increasingly complex as systems integrate more functionality and require ever-increasing levels of performance.

This trend extends to the board-level clock tree that provides reference timing for the system. A “one size fits all” strategy does not apply when it comes to clock tree design. Optimizing clock trees to meet both performance and cost requirements depends on a number of factors, including the system architecture, integrated circuit (IC) timing requirements (frequencies, signal formats, etc.) and the jitter requirements of the end application.

Reference Timing – When to Use a Crystal vs. a Clock

One of the first design considerations is to inventory the hardware design’s reference clock requirements and select the type of reference clocks that will be used for the processors, FPGAs, ASICs, PHYs, DSPs and various other components in the system. Quartz crystals are typically used if the IC has an integrated oscillator and on-chip phase-locked loops (PLLs) for internal timing.

Crystals are cost-effective components that exhibit excellent phase noise and are widely available. They can also be placed in close proximity to the IC, simplifying board layout. However, one of the drawbacks of crystals is that their frequency can vary significantly over temperature, exceeding the parts-per-million (ppm) stability requirements of many serializer-deserializer (SerDes) applications. In many stability-sensitive high-speed SerDes applications, crystal oscillators (XOs) are recommended because they guarantee tighter stability than passive crystals.

Clock generators and clock buffers are typically used when several reference frequencies are required. In some applications, FPGA/ASICs have multiple time domains for the data path, control plane and memory controller interface and require multiple unique reference frequencies. A clock generator or buffer is also preferred when the IC cannot accommodate a crystal input, when the IC must be synchronized to an external reference (source-synchronous application), or when a high-frequency reference not easily generated by a crystal is required.

Free-Running versus Synchronous Clock Trees

Once the hardware design clock inventory has been completed and the crystals have been selected for some of the components, the next step is to select the timing architecture for the remaining clocks: free-running or synchronous. For applications that require one or more independent reference clocks without any special phase-lock or synchronization requirements, XOs, clock generators and clock buffers are the preferred choice. Processors, memory controllers, SoCs and peripheral components (e.g., USB and PCI Express switches) typically use a combination of XOs, clock generators and clock buffers for reference timing in free-running, asynchronous applications.

XOs are preferable when the application requires one to two timing sources, while clock generators and buffers are better suited for applications that need several individual clocks. Clock generators can synthesize multiple clocks at different frequencies, but sacrifice some jitter performance in comparison to clock buffer + XO clock trees. Clock buffers can be used in conjunction with a XO reference to distribute multiple clocks at the same frequency and provide the lowest jitter implementation for a multi-output clock tree.

Synchronous clocking is used in applications that require continuous communication and network-level synchronization, such as Optical Transport Networking (OTN), SONET/SDH, mobile backhaul, synchronous Ethernet and HD SDI video transmission. These applications require transmitters and receivers to operate at the same frequency.

Synchronizing all SerDes reference clocks to a highly accurate network reference clock (e.g., Stratum 3 or GPS) guarantees synchronization across all nodes. In these applications, low-bandwidth PLL-based clocks provide wander and jitter filtering (jitter cleaning) to ensure that network-level synchronization is maintained.

In networking line card PLL applications, specialized jitter attenuating clocks or discrete PLLs with voltage-controlled oscillators (VCOs) are the preferred clock solution for SerDes clocking. For optimal performance, a jitter attenuating clock should be placed at the end of the clock tree, directly driving the SerDes device. Clock generators and buffers can be used to provide other system references.

 

Figure 1. Clock Tree Examples

Next: Clock Jitter

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