Verification challenges of ADC subsystem integration within an SoC
The real world is analog in nature. Any information which needs to be captured from our surroundings is always an analog value. But processing of analog data in a microprocessor requires that the data be converted to its digital equivalent first. For this, different kinds of ADCs (Analog to Digital Converters) are used in an SoC. Depending on a few parameters, namely the throughput, the immunity to noise, and the complexity of design, the type of the ADC is chosen.
An SoC designer is not required to know the deep design intricacies of any IP they are integrating into the SoC. So even from the perspective of an SoC designer, if the ADC is considered as a black box, there are many factors that decide the quality of performance of the ADC at the SoC level. We must take care of these factors.
The conversion of an analog signal into digital data requires discretization in both time as well as amplitude. The discretization in time happens in the sampling phase and the discretization in amplitude happens in the quantization phase. Sampling is done using a sample hold circuit. A sample hold circuit has a switch, a resistive path and a capacitance on which the voltage is sampled when this switch is closed. The quantization in very simple terms is the scaling of the sampled value to a digital value within a range (governed by the reference voltage of the ADC). The sampling and quantization phases are as shown in Figure 1.
Figure 1: Generalized Analog to Digital Conversion Process
Even in the simple black-box picture of an ADC we need to know the following about its integration in the SoC:
- The ADC has multiple input channels and has a single digital output.
- There is a multiplexing between the channels such that at any time the ADC will convert the data coming at one channel.
- There is a clock on which the sampling happens.
- There is a reference that any ADC uses in its quantization phase.
With these considerations we understand that there are many design intricacies and frequently encountered issues with the same, even in such a "simple" external picture of the ADC. We will cover all of them one by one in the following subsections. Figure 2 shows the generic integration of ADC into an SoC.
Figure 2: General integration of ADC into the SoC
Analog Input Channel
In the first phase of conversion, that is, sampling, the analog input coming at the input channel is most important. The sampling capacitor is a part of the ADC design itself but the resistance through which sampling happens is very much SoC integration dependent. There are some very frequently encountered integration particulars that need verification.
It is the resistance of the analog input path which decides how much time will be required for sampling (For the same C the sampling time will increase with increase in R, sampling time being nothing but the charging time of the capacitor). The sampling phase is controlled by a switch. This switch remains closed for a duration which is specified in one of the programmable registers of the ADC IP design.
This means that the time that any analog value gets to be stored in the sampling capacitor is decided from within the ADC design using one programmable register. Let’s call this time Tswitch . At the same time the analog input requires a certain minimum time to charge the sampling capacitor, which is the sampling time (RC) of the capacitor through the resistive path . Let’s call this time Tsampling . For the analog value to get sampled:
Tsampling < Tswitch (Equation 1)
Tswitch is programmed within the ADC IP, but Tsampling is decided solely by the integration. So as SoC designers we have to make sure that Tsampling is minimized. One way of doing this is keeping the resistance of the path at a minimum. In this context refer to Figure 3.
Figure 3: Consequence of giving insufficient time for charging of the sampling capacitor.
We often talk about SNR degradation in the ADC conversion process. The one easily avoidable source of noise to the ADC is the inaccuracy introduced due to insufficient time of the closing of the switch or too high sampling time of the resistive input path of the ADC. Basically Tsampling or Tswitch which does not fulfill the above criteria.