System level design and integration challenges with multiple ADCs on single chip
Automotive MCUs catering to markets such as safety, body and chassis and power-train rely highly on sensors and other peripherals on the board for crucial information. They might need to monitor as many as 100 parameters as shown in Figure 1. Since the majority of these sensors and peripherals send out signals that are analog in nature, it is very well implicit that we need to have an analog to digital convertor to sample all these signals and pass them on to the controller so that it can make meaningful decisions.
Figure 1: List of some sensors that are used across different segments of car
Now an interesting point emerges, to monitor so many channels one would need multiple ADCs. Another constraint that makes issues more complicated is a limitation on the number of ADC channel pins. We might not have hundreds of ADC input pins ported out. Therefore, to monitor hundreds of signals one might start multiplexing a few of these signals onto a single channel of the ADC. From a systems perspective two more important points are worth noting here. For safety features some of the crucial sensor outputs might need to be monitored with multiple ADCs. Such a feature is necessary to maintain redundancy on certain signals in terms of both measurements and connectivity. Secondly, some customers need to monitor important internal channels to check for the correct operation of the SoC. Some of the Power Management signals and certain supplies etc. are measured through the ADC to diagnose the proper working of the SoC.
Based on what has been discussed we understand that we need multiple ADCs in the system and moreover we would need to multiplex the channels of these ADCs to monitor all of them. Once we understand the need from systems level, let's try to analyze the integration challenges that arise in order to connect multiple ADCs on a single chip.
Supply and reference
- As we know that ADC has a reference input voltage against which the analog input voltage is compared so if the reference used for conversion is itself not accurate or noisy the overall accuracy of an ADC cannot be guaranteed. The reference noise must not be comparable to 1/2 LSB to avoid loss of bits in output data. Any type of radiated, conducted or electromagnetic emissions can get coupled to the reference or input voltage which degrade the ADC resolution. In multiple ADC architectures we might not have a dedicated set of supply and reference pins for each of the ADC instances as the number of pins available is always a major constraint. So the ADCs might need to share the supply or the reference. This also affects the static and the dynamic characteristic of the ADC in a maximum throughput (minimum sampling and conversion time with ADC clocking at its maximum frequency) mode. Dedicated supplies for each instance may also not be a good idea at times as the different ADCs may show deviation in their results. The power supply should also have a good regulation, which means that when the load is increased from null to full load, the voltage should remain stable over the entire range.
Placement of ADCs in the floor-plan
- ADCs require very careful consideration in the floor plan. I/O pins such as communication protocol pins e.g. I2C, UART, if placed close to the ADC input channels get coupled through the package and a part of the switching current is transmitted to these ADC pins. This is called I/O crosstalk and acts as a source of noise. Shielding the analog signal by placing ground tracks across it helps reduce noise produced by cross talk etc. Noisy systems like SMPS (due to its internal fast switching power transistors) or pins sitting next to the ADC pins might affect ADC’s performance. Constraining such placement options is easy when we have one ADC in the SoC but it becomes extremely tough to manage the padring and SoC floor plan to keep all the ADCs away from noisy systems while maintaining all the below mentioned constraints. The ADC block must be placed close to the input channel pads. It ensures that metal connections can be drawn easily and there is no congestion in the floor-plan. The routing parasitic can be maintained within the defined specs. The input channels, the supply and reference voltages have a shielding requirement as well which complicates routing to a whole new level.