Further into the alphabet with interleaved ADCs

Jonathan Harris, Analog Devices -December 02, 2013

In my article earlier this year on EDN entitled “The ABCs of Interleaved ADCs” I discussed the basics of interleaving. The many benefits of interleaving were presented which spanned across many market segments from communications to measurement equipment to military/aerospace. Each segment has applications that can benefit from interleaving ADCs. In communications infrastructure there is motivation for higher sample rate ADCs to allow for multi-band, multi-carrier radios. In addition, higher sample rate make way for wider bandwidth that can be used in linearization techniques like DPD (digital predistortion).

In military and aerospace markets, higher sample rate ADCs enable multi-purpose systems for communications, electronic surveillance, and radar. In industrial instrumentation, higher sample rate ADCs enable vendors to design equipment to measure higher speed signals accurately. As is typically the case, we saw there was no such thing as a free lunch. Interleaving ADCs does come with its own set of challenges. There are various mismatches that we see when interleaving ADCs which result in spurs in the ADC output spectrum at fS/2 and fS/2 ± fin. These mismatches are due to differences in the offset, the gain, and the timing between the two interleaved converters. In this article we will dive a little further into the alphabet and go beyond just the ABC’s. We will examine the magnitude of the spurs as a result of the amount of the different mismatches.

First recall that by interleaving two ADCs, the sample rate is increased by a factor of two. This extends each Nyquist zone by a factor of two also, doubling the available bandwidth in which to operate. Notice in Figure 1 the 180 degree clock phase relationship and how the samples are interleaved. The input waveform is alternatively sampled by the two ADCs. In this case, the interleaving is implemented by using a clock input that is divided by a factor of two and the required phases of the clock are routed to each ADC. The increased operational bandwidth brings many advantages to applications across many market segments. Radio systems can increase the number of supported bands; radar systems can improve spatial resolution and measurement equipment can achieve greater analog input bandwidth.

Figure 1. Two Interleaved ADCs – Clocking and Samples

Just as before when starting with the ABCs of interleaving, we will begin by taking a closer look at the offset mismatch spur. As you may recall, the offset mismatch between the two ADCs will produce a spur at fS/2. So how do we know how big this spur is going to be? Let’s take a look at equation 1a below where OffsetMismatch is given in number of codes.

Now, consider we have a typical offset mismatch between two 8 bit ADCs in a dual channel interleaved device, in this case, the AD9286. This is about 0.4 percent of full scale for the nominal value. This means that the number of codes would be 0.4 percent of 28 = 1.024 codes. Substituting this in equation 1b we get the following:

This gives a quite interesting result. An offset mismatch of 0.4 percent of full scale doesn’t seem like much of an error but it results in a fairly large offset spur with a magnitude of –41.94 dBFS. Most applications today for high speed ADCs cannot tolerate this type of spur. This would dominate the spurious free dynamic range (SFDR) for the interleaved ADCs. Most applications require an SFDR of at least 70 dBc, and as much as 85 dBc for multi-carrier GSM (MC-GSM) applications. This is one of several reasons the AD9286 has an offset adjustment that allows the user to fine tune the offset of each ADC to minimize the offset mismatch.

In addition, since the spur’s location is at fS/2, it will likely be filtered with any anti-alias filter (AAF) that is used on the analog inputs of the ADCs. In order to gain some additional insight into the offset spur, Figure 2 below shows a plot of the fS/2 spur with relation to the amount of offset mismatch between the ADCs.

Figure 2. Offset Spur vs Offset Mismatch (Interleaved 8-bit ADCs)

This gives us quite an interesting picture. In order to meet typical spurious requirements of 70 dBc (-71 dBFS), the offset mismatch must be less than 0.025 percent of full scale for an 8 bit converter. It is difficult to make out in the plot, but in order to meet the typical specification for MC-GSM, the offset mismatch must be less than 0.0025 percent. This gives us an idea of how closely the offset needs to be matched. The next step is to now take a look at the math for the gain offset. This will allow us to see how much gain mismatch translates into the interleaving spur at fS/2 ± fin.

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