A novel partitioning strategy for analog routes for hierarchical designs
In the competitive semiconductor world, most organizations try to put numerous applications and features into a single design. To come up with demanding multi-featured designs, SOC’s are becoming extremely complex and there arises a need to design hierarchical SOC’s. In addition, in the automotive world, safety chips are very critical and have stringent requirements with respect to partitions and their routing. Such chips require the partitioned blocks to have analog blocks as well inside them, which make the partitioning with analog routes challenging. In this paper we propose a partitioning approach that helps take care of the complexities that come into picture while integrating these blocks in SOC.
With increasing complexity being introduced into our chips, there is an ever increasing need to make the designs hierarchical, bringing partitions into picture. Such partitions at times need to incorporate analog IP’s and their associated custom routes into them, which talk throughout the chip including pads. In such partitions the analog routes talking from pad to block is divided into two parts, from pad to partition boundary and from partition boundary to block pin shown as A and B in Figure 1 below.
The Conventional Partitioning Approach
Partitioning is a process of dividing the chip into small blocks. This is done mainly to separate different functional blocks and also to make placement and routing easier. Partitioning can be done in the RTL design phase when the design engineer partitions the entire design into sub-blocks and then proceeds to design each module. These modules are linked together in the main module called the TOP LEVEL module. This kind of partitioning is commonly referred to as Logical Partitioning.
At the physical level each block is individually placed and routed (as in a SOC), their Library Exchange Formats (LEFs) then dumped and plugged into chip top. The power/ground rails over the block needs to be drawn in such a way that they align with chip top rails when plugged in SOC.
When analog blocks are a part of these blocks, their respective custom routes are first drawn considering the entire SOC is flattened. And then the LEF of the partition is dumped in a way such that it contains a part of these analog routes and the rest is contained by the SOC. At times this leads to overhanging analog routes in the partition.
Figure 2. Custom Route Overhangs in partition LEF