JESD204B Subclasses (part 1): Intro and Deterministic Latency

-June 18, 2014

1           Introduction

Unquestionably, a hallmark of the Information Age is an explosion in the need to collect, process, and distribute larger and larger chunks of data.  In communications networks, this means more bandwidth for the infrastructure and the components connecting to it.  In the medical industry, this translates into more detailed information from scans, x-rays, and other instruments.  Relatedly, testing and analysis of this rapid expansion in bandwidth translates into the need for higher speed and capacity in electronic test equipment.

This insatiable demand for data is what led to the need for JEDEC to introduce the JESD204 standard for a high-speed serial link between data converters and logic devices.  The “B” revision of the standard, released in 2011, has pushed the serial link data rates to 12.5 Gbps in order to enable the higher bandwidth requirements of today’s converter-based applications.  In many of these applications, there is a need for data to traverse through the system with a known and consistent delay from power cycle to power cycle.  This concept is referred to as “deterministic latency” and provisions for this requirement were introduced in the JESD204B standard as well. 

Prior to the release of this revision, designers of systems needing deterministic latency used external application layer circuitry to realize the requirement.  In the JESD204B standard, 3 subclasses are introduced.  Subclass 0 is intended to be backward compatible with the JESD204A standard and has no provision for implementing deterministic latency.  Subclass 1 introduces an external reference signal, called SYSREF, which provides a system level reference for sample timing.  Subclass 2 defines how the SYNC~ signal can be used as the system level reference for sample timing. 

In each case, it is the sample timing reference that can be used to implement deterministic latency. The intent of this “mini-tutorial” is to clarify the operational distinctions between the three JESD204B subclasses, and to provide the reader with a working knowledge on the implementation of their individual deterministic latency functionality.

Designers of systems needing deterministic latency used external application layer circuitry to implement this requirement prior to the release of this revision.

2           A  Deterministic Latency Overview

The JESD204B standard defines Deterministic Latency (DL) as the time difference between when frame-based samples arrive at the serial transmitter to when the frame-based samples are output from the serial receiver.  Latency is measured in the Frame Clock domain and must be programmable in increments at least as small as the Frame Clock period.  The latency must be repeatable from power-up cycle to power-up cycle as well as with any resynchronization event.  This definition is illustrated in Figure 1

Figure 1.  Deterministic Latency Illustration

The deterministic latency in a JESD204 system consists of fixed delays and variable delays.  Variable delays are the result of arbitrary phase relationships from power cycle to power cycle between clock domains in the digital processing blocks. In JESD204A and JESD204B subclass 0 systems, the variable delays cannot be accounted for.  Therefore, there is a power cycle variation in the latency across the link.

Next: 3 Subclass 0

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