JESD204B Subclasses (part 2): Subclass 1 vs. 2, System Considerations
In “JESD204B Subclasses (part 1): An Introduction to JESD204B Subclasses and Deterministic Latency” a summary of the JESD204B subclasses and deterministic latency was given along with details regarding an application layer solution for multi-chip synchronization in a subclass 0 system. Part 2 of the series takes a closer look at the differences between subclass 1 and subclass 2. In particular, we will look at the challenges to meeting the deterministic latency related timing requirements, device clock speed limitations in subclass 2, and guidelines on which subclass is best for a given system application.
2 Subclass 1
In a subclass 1 system, the accuracy of the deterministic latency depends on the timing relation between device clock and SYSREF and the distribution skews of these signals within the system. In addition to the setup and hold time requirements for SYSREF (TSU and THold), the application’s tolerance for deterministic latency uncertainty will be critical in defining the application’s distribution skew requirements for SYSREF and device clock.
2.1 Capturing SYSREF accurately
Converters employing the JESD204B interface sample data at a very high rate. In order to reduce phase noise in the system, it is common for these converters to use a reference clock, which is the same as the JESD204 device clock, that is at or above the sample rate. In many cases, this clock is in the GHz range. At these speeds, meeting the setup and hold time requirements become very challenging. To ease the system design, it may be necessary for the phase offset of SYSREF and/or device clock to be programmable for each device that is part of the JESD204B system.
One advantage that subclass 1 has over subclass 2 is that it uses source synchronous clocking. A subclass 2 system uses system synchronous clocking and will encounter frequency limitations sooner than that of one that uses source synchronous clocking. This will be demonstrated when we take a closer look at specific subclass 1 and subclass 2 timing examples.
2.2 Deterministic Latency Uncertainty
Deterministic latency uncertainty (DLU) is the LMFC skew in the JESD204B system and is determined by the difference between the earliest and latest possible capture of SYSREF in the system. Figure 1 illustrates the worst-case DLU which occurs when setup and hold time requirements for SYSREF capture are not met at every device in the system. This occurs when the distribution skew of the device clocks in the system are not controlled and creates up to one device clock (DCLK) of uncertainty. This is added to the SYSREF distribution skew (DSSYSREF) to produce the total DLU.
DLU = DSSYSREF + TDCLK
DSSYSREF is the difference in the arrival time of the earliest arriving SYREF in the system (across all devices in the system) and the last arriving SYSREF. In the illustration, TSU is ½ TDCLK and THold is ¼ TDCLK. The earliest arriving SYSREF (A) is captured at the earliest possible time (DCLKA just meets the setup time requirement) while the last arriving SYSREF (N) is captured at the latest possible time (DCLKN just misses the setup time requirement). So the corresponding LMFC’s are miss-aligned by DSSYSREF + TDCLK.
Figure 1. Worst-case Deterministic Latency Uncertainty
In many applications, the requirements for DLU are such that this worst-case scenario is acceptable. For these applications, it may not be necessary to tightly control the device clock distribution skew. Ensuring the pulse width of SYSREF is ≥ (2 x TDCLK) and controlling the SYSREF distribution skew to meet the system timing requirement should be adequate.
In applications where the additional device clock of uncertainty is not acceptable, then the device clock distribution skew must be tightly controlled to ensure that the timing requirements for SYSREF are met at each device in the system. This case is illustrated in Figure 2 and the uncertainty is given by the equation:
Figure 2. DLU while meeting setup and hold time for SYSREF