Implementing an SLVS transceiver
Although the company crafted the technology for easy implementation in the equipment of a previous decade, it has its limitations. Addressing the limitations of LVDS as a generic standard, several variations have evolved to meet application-specific requirements. In October 2001, the JEDEC (Joint Electron Device Engineering Council) Solid State Technology Association published the SLVS (scalable-low-voltage-signaling) standard for 400-mV operation. SLVS inherits from LVDS low noise susceptibility. It also boasts a scaled-down 400-mV signal swing—versus the 700-mV swing of LVDS—and includes a ground reference. This combination results in lower power consumption for transmission. The interface normally requires a 0.8V power rail, which is commonly available in submicron silicon devices. Designers can achieve a data rate as high as 3 Gbps or beyond over a range that is compatible with the size of a typical PCB (printed-circuit board). This combination of features makes SLVS appropriate for use in high-speed, low-power transmission for interdevice data links on a PCB.
This utility also makes SLVS important in the FPGA world. Designers often use FPGA devices, due to their feature-rich I/O ports, for datapath interfacing and protocol bridging. With the increasing popularity of SLVS in data-channel design, designers hope to achieve economic and robust FPGA design for SLVS-transceiver applications. Most FPGAs support the traditional LVDS interface. However, designers cannot program all modern FPGA-I/O structures to drive current at SLVS requirements for output, and not all provide a built-in differential termination to receive SLVS input with few external components. To determine the abilities of an FPGA-I/O design to support SLVS, you must look deeper into both the standard and the I/O structures that today’s programmable devices use.
The LVDS data-transmission standard is a mature technology and has become the most common transceiver interface in applications such as video, storage, and data communications, which require transmission of large amounts of data. In a point-to-point LVDS link, a current source in the transmitter toggles polarity as the signal changes state, driving the wire loop (Figure 1). Most of the drive current flows through the receiver-side termination resistor, assuming high impedance at the op amp’s input for dc current. The voltage drop across the termination resistor is proportional to the drive current; when the transmitter toggles, the receiver’s op amp detects the change in polarity, recognizing the change in signal state at the transmitter’s input.
LVDS offers high noise tolerance because it uses a pair of differential traces to provide common-mode rejection. Both the speed of data transmission and the power dissipation closely relate to the voltage swing across the termination resistor, which is 350 mV, or 700 mV p-p nominal, over a 100Ω resistor for a typical LVDS loop.
LVDS channels have a low susceptibility to external noise because distant noise sources tend to add the same amount of voltage to both lines, so the difference between the voltages remains the same. The low common-mode voltage is the average of the voltages on the two traces—approximately 1.25V. The transmitter sets the common-mode voltage as an offset voltage from ground. The 350-mV differential voltage causes the LVDS to consume static power in the LVDS load resistor, depending on the 1.25V offset voltage and 350-mV differential-voltage swing.
The JEDEC JESD8-13 SLVS-400 standard defines a point-to-point signaling method. SLVS uses smaller voltage swings and a lower common-mode voltage than LVDS. The 200-mV, or 400-mV-p-p, SLVS swing contributes to a reduction in power and is common in RSDS (reduced-swing-differential-signaling) standards. The RSDS standard reduces the swing from 350 mV to 200 mV with the same 1.25V common-mode offset of the LVDS standard. SLVS goes further and also reduces the common-mode voltage. The SLVS nominal common-mode voltage of 200 mV provides a considerable decrease in quiescent power. The combination of a smaller signal swing and low common-mode voltage produces much lower power consumption.
To illustrate this point, consider that a 6-Gbps LVDS SERDES (serializer/deserializer) link consumes approximately 250 mW. A typical SLVS pair running at 800 Mbps consumes approximately 15 mW. Even eight 800-Mbps SLVS links running in parallel for a combined speed of 6.4 Gbps consume only about 120 mW—less than half the power consumption of the LVDS implementation.
FPGA design for SLVS
To build an SLVS-compatible interface, a designer must consider whether the target FPGA device provides sufficient hardware resources and flexibility at its I/O ports for both receiver and transmitter implementation. Embedded differential termination is preferable in an SLVS receiver to minimize the number of onboard components that directly connect to its transmitter peer. More important, many FPGA receivers target use in LVDS, so designers should ensure that the FPGA receiver’s differential and common-mode range covers the entire SLVS output specification. The FPGA’s differential output port also must be able to source the drive current for the proper SLVS level with an external coupling-resistor network.
The SLVS interface finds application in, for example, data communications and video/image displays requiring high-speed and low-power data channels. An FPGA device with SLVS-compatible transceivers plays an important role in bridging the SLVS I/O on a standard IC product to other data protocols. The recent design-in of a Lattice SC/M FPGA with a Broadcom VDSL2 (very-high-bit-rate-digital-subscriber-line) reference line card demonstrates how the FPGA provides SLVS interfacing and XAUI (10-Gbps-attachment-unit-interface) PHY (physical)-layer bridging functions.
On the VDSL2 reference design, the FPGA implements six SLVS links (Figure 4). The FPGA device functions as a bridge between the SLVS data stream and the XAUI packets. The VDSL2 device transmits three links and receives three links. Each link contains an 18-bit bus, connecting to the standard SLVS ports from Broadcom’s DSL (digital-subscriber-line)-termination ICs to the FPGA. The FPGA can steer and multiplex the SLVS buses from any of the three receiver links to any of the three transmitter links, so the Broadcom devices all interconnect. At the other side of the FPGA, eight 3.125-Gbps SERDES channels can form two interfaces for Ethernet-switch connections. This configuration constructs a typical 48-line VDSL2 terminal in a 10-Gbps backhaul connection.
A number of features, including low differential-mode signal swing and low common-mode voltage, provide lower power dissipation for SLVS ports than that of LVDS ports. This advantage is leading to wide use of SLVS within the communications/networking community, especially on the latest generation of SOCs (systems on chips). FPGAs provide a flexible and economical implementation for a data-transmission interface and for protocol bridging, so it is important for designers to understand how to implement an SLVS interface in an FPGA. Design engineers should carefully consider an FPGA’s I/O features and select the right device from commonly available LVDS-compatible systems to implement the lower-power SLVS interface. Features such as wide input common-mode range, built-in differential-termination load, programmable SLVS drive-current output, and high SERDES-to-logic ratios can have a substantial effect on board-level implementation of SLVS links.