Tablet and smartphone demand drives new trends in mobile memory
Janine Love, Editor, Memory Designline - July 28, 2011
As the number of mobile devices worldwide
surges, the need for better, cheaper memory
for these devices soars. Numerous alternatives
are available for mobile memory. Industry
standards abound, and others are still in
development. By all accounts, this market is
on the upswing, so where do all of the memory technologies and
form factors fit in, and what’s on the horizon for mobile memory?According to estimates from IHS iSuppli Research, the growth of sales for smartphones and tablets will increase revenue in the mobile-memory market by 26% in 2011 to $16.4 billion, compared with $13 billion in 2010 and, iSuppli projects, $19.3 billion in 2012 (Reference 1). Gregory Wong, principal analyst at Forward Insights, agrees that consumer devices, particularly smartphones and tablets, are driving memory demands. He observes two basic types of memory available for these devices: e•MMC (embedded multimedia card), a low-power JEDEC (Joint Electron Device Engineering Council) Solid State Technology Association standard, and solid-state drives. Solid-state drives offer better IOPS (input/output operations per second) for tablets than does the JEDEC standard but at a higher cost and power consumption (Figure 1).
Increasing performance and maintaining
low power are the major challenges
for memory designers, and many
see universal flash storage, which
accomplishes these goals, as the next big
thing. Vendor support is weaker than
it was when JEDEC first proposed the
standard, according to Wong. As such,
a solid-state drive with a low-power
SATA (serial-advanced-technology-attachment)
interface could be an alternative.
“For example, the idle power of
the SATA PHY [physical layer] is quite
large,” he says. “You could make it ‘low
power’ by turning off the PHY when
[it is] idle.”Setting the standards
JEDEC, a volunteer organization, sets open standards for the microelectronics industry and recently hosted a standardization meeting in Vancouver, BC, Canada, focusing primarily on memory-related topics. “The ongoing standards-development work within the JEDEC committees, focused on mobile memory, has significant strategic value to the industry and will help make possible a wide range of innovative new products,” says Desi Rhoden, chairman of the JC-42 Committee for Solid State Memories. Published JEDEC standards that relate to mobile memory include LPDDR2 (low-power double data rate 2), universal flash storage, and e•MMC.
JEDEC designed the LPDDR2
JESD209-2E standard to enhance the
design of mobile devices, such as smartphones,
cell phones, PDAs (personal
digital assistants), GPS (global-positioning-system) units, and handheld
gaming consoles, by enabling increased
memory density, improved performance,
greater compactness, overall reduction
in power consumption, and longer battery
life. As a result, it offers advanced
power-management features, a shared
interface for nonvolatile and volatile
memory, and a range of densities and
speeds. The JC-42.6 Subcommittee for
Low Power Memories published the
standard in April 2009 and updated it
in April 2011.The JEDEC JESD220 universal-flash-storage standard targets both embedded and removable flash-memory-based storage in mobile devices that require high performance and low power consumption, such as smartphones and tablets. The standard uses the MIPI (Mobile Industry Processor Interface) Alliance’s M-PHY (MIPI-physical-layer) and UniPro (Unified Protocol) specifications to form its interconnect layer. Because it combines this advanced interface with low active-power level and a near-zero idle-power level, universal flash storage shows promise in achieving significant reductions in device power consumption. JEDEC first published the standard in February 2011.
In June, JEDEC announced the publication of the JESD84-B45 Embedded Multimedia Card Electrical Standard Version 4.5, a low-cost data-storage and communication standard that targets applications such as smartphones, cameras, organizers, PDAs, digital recorders, MP3 players, pagers, and electronic toys. The latest version of the standard increases interface bandwidth from 104 Mbytes to 200 Mbytes to achieve high mobility, high performance, low power consumption, and high data throughput. This free standard helps to improve the interaction between the host processor and the memory device at the interface, configuration, and protocol levels to gain system performance and reliability (Reference 2).
JEDEC is also developing LPDDR3 to meet the higher bandwidth requirements of next-generation smartphones and tablets. JEDEC LPDDR3 effectively extends the LPDDR2 standard’s bandwidth, reaching 6.4 Gbytes/sec and allowing 12.8 Gbytes/sec for a dual-channel configuration. It will support both POP (package-on-package) and discrete packaging types and preserve the power-efficient features and signaling interface of LPDDR2.
The JEDEC WideIO (wide-input/output) standard aims to satisfy industry demands for increased levels of integration and improved bandwidth, higher latency, lower power consumption, lower weight, and smaller form factor. JEDEC expects WideIO to provide performance, energy efficiency, and compactness for smartphones, tablets, handheld gaming consoles, and other high-performance mobile devices. WideIO mobile DRAM uses chip-level 3-D stacking with TSV (through-silicon-via) interconnects and memory chips on SOCs (systems on chips). WideIO will suit use in systems that require memory bandwidth as high as 12.8 Gbytes, including 3-D gaming, 180p high-definition video, and similar applications.
In the field
Designers selecting mobile memory care about performance, form factor, and supply availability. According to Scott Nelson, vice president of Toshiba’s memory business unit, NAND is the de facto storage medium for mobile memory because of density and low cost. He sees designers of mobile devices selecting NAND memory across a range of formats—from raw NAND, embedded memory with an embedded multimedia-card interface, to removable memory, such as SD (secure digital) and microSD.
One of the challenges for memory
providers is the continuing need for
improved error correction in next-generation
NAND. In response, Toshiba
offers an approach that addresses
increasing needs for better ECC (error-correction
code) and flash management.
The company also offers the
SmartNAND MLC (multilevel-cell)
NAND product, which is essentially
NAND with an ECC-controller chip
(Figure 2).Tetsuya Yamamoto, a Toshiba memory-engineer manager, observes that performance needs increase with each generation of JEDEC specification, which is an additional challenge. For instance, the most recent Embedded Multimedia Card specification raises performance to 200 Mbytes/sec. Yamamoto expects the universal-flash-storage standard to include a maximum speed of 2.9 Gbytes/sec. To address the performance issue, Toshiba plans to support a universal-flash-storage interface in addition to the one for the Embedded Multimedia Card.
According to Kendra De Berti,
senior marketing manager for Rambus,
the memory needs of smartphones and
tablets represent a challenging mix,
including low active and standby power,
fast power-state transitions to increase
battery life, small footprint, high bandwidth,
multiple memory channels for
high throughput, and the ability to support
more powerful multicore processors.
She notes that engineers must now
create low-risk memory that uses and
maintains backward compatibility with
the infrastructure.

To address these challenges, Rambus
has been building a patent portfolio for
mobile memory with several proprietary
technologies in the Mobile XDR
(extreme-data-rate) memory architecture
(Figure 3). For example, the company’s
low-swing differential-signaling
technique delivers high data-rate performance
at low voltage. Rambus has
heavily invested in JEDEC’s LPDDR2/3
standards, which use single-ended signaling,
in which data and command/address signals are referenced to ground.Rambus is closely following the
emerging WideIO specification. “The
promise of WideIO DRAM with TSVinterconnect
technology is high bandwidth
at low power in a compact footprint,
and it would address the major
shortcomings of the LPDDR, but it
does so by introducing major issues of
its own,” says De Berti. She sees the
need for significant development work
before Rambus can supply WideIO with
TSV technology with high yields and
low costs. Further, she adds, significant
changes to supply chains and business
models will be necessary for broad adoption
in mixed-IC, processor-plus-memory,
implementations.
You can reach
Designline Editor
Janine Love at editor@writesol.com. Read more at www.eetimes.com/design/ memory-design. |
| References |
|
| For More Information | ||
| Forward Insights | IHS iSuppli Research | Joint Electron
Device Council Solid
State Technology
Association |
| Mobile Industry
Processor Interface
Alliance | Rambus | SanDisk |
| Toshiba |
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