The Class i low-distortion audio output stage (Part 4)
Kendall Castor-Perry - November 26, 2012
In the final part of his series on a new ultra-linear audio output stage driver, Kendall Castor-Perry presents simulations of its static and dynamic linearity performance, demonstrating the inherent manufacturability and freedom from crossover distortion, without need for excessive standing currents.
Part 1 looks at the core problems of push-pull audio output stages and how they might be improved upon. Part 2 introduces the driver circuit for the "Class i" output stage. Part 3 examines the linearity performance that's available from this configuration.
Figure 10 shows that the act of pulling large currents out from the output devices does not significantly change the inherent voltage gain of the stage. The peak to peak gain variation is less than 0.002%. In this plot, the output stage is not yet being presented with a resistive load, which is why the small signal gain is so close to unity.
Figure 10: Variation of small signal gain over ±30 V, load current stepped -8 A to +8 A.
Figure 11 shows a plot of the simulated output impedance with injected output current of -8 A to +8 A and the static voltage stepped from -30 V to +30 V. The wobble in the output impedance curve looks alarming until you check the scale; it is ±0.16 mohm, equivalent to a peak linearity error of less than ±0.004% into 4 ohms.
The rapid deviation in output impedance happens only when the conducting half has almost the full supply voltage across it. This only happens when driving the amplifier into a negative resistance load (one of the pathological tests that amplifier designers love). A significant takeaway from figure 11 is that gm-doubling is completely absent over the entire current and voltage range.
Figure 11: Output resistance, input voltage stepped -30 V to +30 V.
The detailed shape of this plot is very dependent on the simulation models used for the transistors in the long-tailed pair. The observant may notice that the ‘wobble’ is antisymmetric about zero, which is unusual for a symmetrical circuit. This is due to mismatch between npn and pnp small-signal devices. It’s instructive (but unrealistic) to construct perfect pnp simulation complements for the npn devices used (just copy/paste a new device into your library, change its name suitably, and change the type from NPN to PNP). In such cases, the error curves become symmetric around zero.
We can exercise the circuit with a sinewave of progressively increasing level and take an FFT to get an estimate of distortion levels. Figure 12 shows the FFT result for a 1 kHz sine tone applied at the input with peak levels between 200 mV and 20 V. Worst-case is at 2 V (this is 0.5 A peak into 4 ohms; compare figure 11) where the 2nd harmonic is 95 dB down on the fundamental. When overdriven, the circuit clips cleanly at around two diode drops from each rail.
Figure 12: 1kHz sine and the first 4 harmonics (note the scale).
The main residual sources of non-linearity in this simulation are non-ideality in the transistor models (particularly in the Class i doublet), model mismatches between pnp and npn small signal devices, and offset voltage changes caused by the difference in Is matching between the input transistors. Naturally, when building a practical amplifier to deliver this level of linearity, careful measurement and device selection will be required. Simulation can only take us so far.
As drawn, the input doublet experiences the difference between the input voltage and its local supply voltage. As this varies with applied signal, the Vbe for a given current level changes. The approach used here is to select devices whose model declares a high value of the Early voltage parameter VAF. Suitable devices with VAF~450 were chosen from the large range of devices by Diodes, Inc. These appear to give good enough performance that the extra complexity of cascoding is unnecessary.