Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond

-February 20, 2013

Industry Need for Continued Scaling
Technological advances in transistor scaling have had a dramatic effect on consumer electronics and their corresponding use cases. In 1973, Motorola developed the first mobile phone, which weighed 2.5 pounds, was 9 inches long, had limited battery life and only allowed users to make and receive calls. Fast forward to today's mobile devices that fit in the palm of your hand, with batteries that last all day and more computing power than ever thought possible.

While it has taken 40 years to come this far, innovation has been exceptionally rapid over the course of the past 10 years, and consumer expectations have accelerated at a similar pace. What sort of features and computing capabilities will we expect of our mobile devices five years from now? How about in 10 years? Future improvements largely hinge on the industry's ability to continue on the path of Moore's Law by producing ever-smaller transistors with ever-greater performance. Satisfactory scaling fulfills two core requirements: the need for smaller transistors that reduce costs and a parallel need for improved performance and lower power consumption.

To date, transistor scaling has continued in accordance with Moore's Law down to 32 nm. Engineering challenges, however, are forcing chipmakers to compromise performance and power efficiency in order to reach smaller nodes - unless they switch to new technologies that help better solve these challenges. Today, the semiconductor industry is starting to deploy such new technologies, largely relying on "fully-depleted" transistors for continued scaling and performance gains.

Fully Depleted Silicon Technology
A fully depleted (FD) transistor can be planar or tri-dimensional. In each case, in direct contrast with other technologies commonly used today, the current between source and drain is allowed to flow only through a thin silicon region, defined by the physical parameters of the transistor.

In the planar design of fully depleted technology, transistors are built flat on the silicon. For the three-dimensional alternative, manufacturers fabricate thin vertical "fins" of silicon in which current will flow from source to drain. Additionally, FD transistors can eliminate the need for implanting "dopant" atoms into the channel. These improvements help chipmakers secure gains in both energy efficiency and performance that are required from scaling silicon technology.

Figure 1: Top Left (1a): Cross-section of a conventional MOS transistor on bulk silicon, Top right (1b): Cross-section of a planar fully-depleted transistor (FD-SOI), Bottom (1c): Perspective view of a FinFET (one fin shown here), silicon-on-insulator and bulk silicon flavors. (*) Note: PTS in the bottom right diagram is Punch Through Stopper, which is a heavily doped barrier layer at the bottom of the fin. S is Source, G is Gate, D is Drain of CMOS transistors. Notional views only; dimensions are not to scale.

In Figure 1a representing a conventional CMOS transistor, the extension of the depletion zone is a function of doping and is variable (modulated by the drain voltage). Its extent correlates well with the notorious "short channel effects" which severely affect the behavior of the transistor.

In contrast, FD transistors, illustrated in figures 1b and 1c, differ from traditional transistor architectures by having a channel that is not defined by its doping level, but rather by physical boundaries - in which case the depletion zone fills the full body of the transistor. This design improves gate control over the channel, which enhances performance and cuts leakage.

Three-dimensional FinFET architectures are in the short-term planning phases of several world-leading foundries to scale CMOS technology to 16 nm and beyond, with the most aggressive schedules aiming for high-volume production no later than 2015, despite the challenges of manufacturing this technology.

For planar architecture, FD-SOI is currently being implemented at the 28-nm node by industry-leading companies such as ST Microelectronics and its partner ST-Ericsson. Allowing for a smooth evolution from conventional planar CMOS technology, FD-SOI is a comparatively simple technology, with its proponents arguing that both power consumption and performance figures are comparable to those of FinFET.

One aspect to keep in mind when considering scaling options is lithography. The need to print smaller dimensions in order to fabricate advanced chips is dramatically increasing the cost of lithography and its share in the overall process cost. To make things worse, beyond 28nm, sophisticated and costly multi-pass patterning, such as double patterning, is required to continue using existing lithography equipment based on 193nm wavelength light sources.

Upcoming lithography based on Extreme Ultra-Violet (EUV) wavelength light sources will have the ability to print tiny dimensions in a single pass, but volume production using EUV technology is not expected for several years. These soaring costs are prompting some companies to think twice before moving their chips to smaller nodes and to seriously evaluate alternatives that offer immediate, competitive results for lower R&D and manufacturing costs. In this context, 28nm planar FD-SOI technology can be a smart choice to obtain next-generation performance and energy efficiency without rushing to 20nm or 14nm.

Figure 2: Two options of starting wafers (outline views, dimensions not to scale). Left: Bulk silicon starting wafer, used for conventional CMOS or FinFET/bulk technology. Right: Silicon-on-insulator starting wafer, used for planar FD-SOI or FinFET technology. Top silicon and buried oxide requirements (thickness, uniformity, etc.) are different for planar FD-SOI and FinFET. Soitec's FD-2D and FD-3D product lines serve FD-SOI and FinFET, respectively.

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