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IC Design

Suzanne Deffree
Editor
Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, related semiconductor manufacturing, and the design methodologies other IC designers are using to become successful.

Challenges in LBIST validation for high reliability SoCs

The challenges of developing LBIST tester patterns for production, and ways of creating such patterns efficiently. Read More...

Design clock controllers for hierarchical test

Get the most out of hierarchical test by adding an on-chip clock controller. Read More...

Cadence unveils Protium FPGA-based SoC prototyping platform

Protium puts two to eight Virtex-7 FPGAs under the hood to help you prototype & test complex SoCs. Read More...

NVM IP offers 75% area reduction

The non-volatile memory IP meets stringent automotive Grade 0 temperature and AEC-Q100 quality requirements. Read More...

MBIST verification: Best practices & challenges

Verification of functioning MBIST is an essential part in any SoC design cycle. Read More...

Quantus QRC tears through extractions

Cadence's update to QRC, Quantus QRC, makes full use of your expensive server hardware, and can speed through extraction five times faster. Read More...

CDC verification of billion-gate SoCs

This article describes three different clock domain crossing (CDC) verification methodologies and how they can best be used in verifying SoCs being designed today. Read More...

Reduce SoC verification time through reuse in pre-silicon validation

This paper demonstrates a methodology to bridge the gap between SoC verification and pre-silicon validation and significantly reduce the debug effort and run-time of the verification sequences. Read More...

Pitfalls of state-transition clock gating

Blindly applying clock gating can result in the exact opposite of the desired effect. Read More...

A robust scan insertion methodology

Designers face multiple challenges in stitching the flops in SoCs to enable robust scan across all process voltage temperature corners. Read More...

DAC2014 Verification view

A look at the hustle, bustle, and acquisitions happening around DAC, with an eye to verification. Read More...

FPGA boards under $100: Introduction

I’m kicking off a major series of hands-on reviews of sub-$100 FPGA boards, so hop on “board” as we start our exploration. Read More...

Spare cell leakage minimization in physical design, part 2 of 2

Pay attention to small details to reap power savings through leakage reduction. Read More...

Spare cell leakage minimization in physical design, part 1 of 2

Pay attention to small details to reap power savings through leakage reduction. Read More...

JESD204B Subclasses (part 2): Subclass 1 vs. 2, System Considerations

Part 2 of the series takes a closer look at the differences between subclass 1 and subclass 2. In particular, we will look at the challenges to meeting the deterministic latency related timing requirements, device clock speed limitations in subclass 2, and guidelines on which subclass is best for a given system application. Read More...

Enhanced timing closure using latches

Latches are generally used in scan timing paths to provide robustness with respect to variations. Theoretically, latches can also be inserted in functional paths provided certain design conditions are ensured. Read More...

JESD204B Subclasses (part 1): Intro and Deterministic Latency

The intent of this “mini-tutorial” is to clarify the operational distinctions between the three JESD204B subclasses, and to provide the reader with a working knowledge on the implementation of their individual deterministic latency functionality. Read More...

Efficiency and memory footprint of Xilkernel for the Microblaze soft processor

The use of a real-time multitasking kernel simplifies the design process of embedded software, but the kernel requires some portion of system's resources. This paper describes results of research work performed to determine overheads incurred by Xilkernel, a real-time multitasking kernel developed by Xilinx. Read More...

Get smarter about production outlier removal

Part average testing is getting an upgrade that can help reduce yield losses because of device outliers without sacrificing quality. Get ready for PAT 2.0. Read More...

Logical chain-based clock implementation

A solution restrategizes timing optimization to tackle clocks and data logic concurrently. Read More...

>> SEE ALL

Single-cycle logarithms & antilogs

Here are some very fast log (and antilog) blocks well-suited to FPGA implementation. Read More...

Build a UWB pulse generator on an FPGA

Make pulses that reach twice an FPGA's clock frequency. Read More...

SDRAM interface slashes pin count

Many designs need deep buffering but don't require ultrahigh-memory bandwidth. Examples include image and audio processing, as well as some deep-FIFO applications. These designs often use a singlex8 SDRAM device that connects to an FPGA or ASIC. This approach solves the buffering problem but also burns a lot of valuable pins, which can be as many as 27 for a single SDRAM device. Read More...

Differential amp has 6dB lower noise, twice the bandwidth

Differential/instrumentation amp topologies possess varying trade-offs. Here’s one that improves noise & BW at the expense of input resistance. Read More...

Design provides single-port-to-dual-port SDRAM converter

Read and write operations won't interfere with each other. Read More...

Compute a histogram in an FPGA with one clock

Use a histogram to analyze large amounts of data. Read More...

PRBS generator runs at 1.5 Gbps

FPGA and serializer generate fast sequences to test communications links. Read More...

VHDL program enables PCI-bus-arbiter core

A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters. Read More...

Postprocessing converts Spice to RF analyzer

Designers of RF and high-frequency products need a simulator that can predict noise figure at a given frequency, minimum noise figure, optimum reflection coefficient for noise, and noise resistance. Read More...

Decode a quadrature encoder in software

Use a microcontroller to decode signals without the need for a dedicated IC. Read More...

Capacitive touch switch uses CPLD

Using an Altera MAX IIZ CPLD, you can implement a touch-switch decoder with no external components. Read More...

Swapping bits improves performance of FPGA-PWM counter

A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC. Read More...

Active multiplexing saves inputs

Add an inverter to reduce current and diodes to route inputs to a microcontroller's inputs as needed. Read More...

Perform hexadecimal-to-BCD conversion in firmware

Converting in firmware eliminates a conversion chip. Read More...

Implement a simple digital-serial NRZ data-recovery algorithm in an FPGA

A shift register and some logic lets you recover embedded clocks from data streams. Read More...

ADC for programmable logic uses one capacitor

Use a capacitor's charging and discharging time to sense a user input. Read More...

Stepper-motor motion controller and driver fit into a CPLD/FPGA

A CPLD or FPGA can be a home for a stepper-motor motion controller and driver. Read More...

Implement a stepper-motor driver in a CPLD

Replace a hard-to-find stepper-motor-driver IC with a programmable-logic device. Read More...

Add a Schmitt-trigger function to CPLDs, FPGAs, and applications

For slow-slewing signals, hysteresis solves trigger problem. Read More...

Three-phase digital-signal generator sweeps frequency

Use a clock divider to sweep frequency by 20 kHz. Read More...

>> SEE ALL

Cadence unveils Protium FPGA-based SoC prototyping platform

Protium puts two to eight Virtex-7 FPGAs under the hood to help you prototype & test complex SoCs. Read More...

NVM IP offers 75% area reduction

The non-volatile memory IP meets stringent automotive Grade 0 temperature and AEC-Q100 quality requirements. Read More...

Quantus QRC tears through extractions

Cadence's update to QRC, Quantus QRC, makes full use of your expensive server hardware, and can speed through extraction five times faster. Read More...

FPGA boards under $100: Introduction

I’m kicking off a major series of hands-on reviews of sub-$100 FPGA boards, so hop on “board” as we start our exploration. Read More...

iPad app from NI runs accurate SPICE simulations

Multisim Touch simulates circuit designs anywhere, anytime, says National Instruments; students, hobbyists and engineers can use the iPad app to design and simulate circuits using high-fidelity SPICE simulation with results identical to the desktop. Read More...

Path Finder mates PCB, IC package, & system design

The Xpedition Path Finder suite provides a single environment that gives cross-domain design teams the ability to model every device/interface. Read More...

IP for PHY connection to Hybrid Memory Cube is certified Compliant

Semtech's Snowbush family of 28-nm Platform Physical Layer IP offers support for the Hybrid Memory Cube specification for ultra fast, next-generation memory. Read More...

Dual-mode Soft IP core supports UART and FIFO operation

Digital Core Design has announced its D16950 soft IP core, featuring functional compatibility with the OX16C950 and an ability to support serial transmission in UART and FIFO modes. Read More...

I2C device interface IP for FPGA requires no programming

Digital Core Design has created DI2CSB -- an I2C slave base IP Core that doesn't need to be programmed. Read More...

Cypress adds entry-level chips to mixed-signal programmables

Expanding the PSoC 4 architecture with entry-level PSoC 4000 devices, Cypress has configured a family of low-cost ARM Cortex-M0 cores integrated with the CapSense, capacitive sensing system. Read More...

LPDDR4 IP offers 3200 Mbps performance

Synopsys LPDDR4 IP offering includes DesignWare LPDDR4 multiPHY, Enhanced Universal DDR Memory Controller and verification IP as well as hardening and signal integrity services Read More...

Streamline DDRx interface design with TimingDesigner/Sigrity melding

DDR design, especially DDR4, needs all the help it can get. Read More...

Companion FPGA packs 85K LUTs in 10x10mm package

The ECP5 FPGA Family was specifically designed to focus on key fast growing and high-volume markets such as small-cells, microservers, broadband access, or industrial video. Read More...

Software library enables FPGA-based drive control

The XSG AC Motor Control Library from software tool vendor dSpace speeds the development of Xilinx FPGA-based motor control designs. Read More...

Debugger teams with ARM’s System Trace Macrocell

Enhancements to Asset InterTech’s Arium hardware-assisted SourcePoint debugger optimize the processing of ARM’s System Trace Macrocell (STM), which provides developers of multicore, multithreaded SoCs a system-level perspective of trace data. Read More...

Software eases interconnect analysis of ARM-based SoCs

Interconnect Workbench from Cadence provides interconnect performance analysis and verification of SoC (system-on-chip) devices incorporating ARM CoreLink CCI-400, NIC-400, NIC-301, and ADB-400 system intellectual property (IP). Read More...

Hypervisor delivers security for multicore processors, enables multi-OS consolidation

Mentor Graphics has introduced an embedded hypervisor product for in-vehicle infotainment systems, telematics, advanced driver assistance systems, and instrumentation. Read More...

FastSPICE simulator offers up to 10X faster throughput

Cadence has introduced Spectre XPS (eXtensive Partitioning Simulator), featuring a breakthrough partitioning technology, that enables higher capacity and faster simulation while requiring two to three times less system memory. Read More...

Synopsys aims at TVs with ARC-based Dolby MS11 decoder

Synopsys' DesignWare IP for ARC Audio Processors has been augmented with support for Dolby Laboratories' Multistream Decoding, expanding the portfolio of ARC audio codecs. Read More...

System builder design tool targets ARM-based SmartFusion2 SoC FPGAs

Microsemi's System Builder is a new design tool within the Libero System-on-Chip (SoC) Design Environment version 11.0 and is specifically targeted at accelerating customer definition and implementation of ARM-based systems using SmartFusion2 SoC FPGAs. Read More...

FPGA/SoC families debut with performance boost, power reduction

Altera has announced its Generation 10 family comprising its Arria 10 and Stratix 10 series of FPGAs and SoCs. Read More...

Requirements lifecycle management tool targets safety-critical FPGA and ASIC design

Aldec's Spec-TRACER is a requirements lifecycle management solution for use in safety-critical industries in which rigorous certification standards exist; such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear. Read More...

Virtex 7-based FPGA module targets multi FPGA prototyping

Pro Design has added the proFPGA V7 mini FPGA module to its family of FPGA based prototyping solutions. Read More...

EDN Hot 100 products of 2012: EDA/IP and memory/storage

This section of EDN's Hot 100 Products of 2012 includes design automation software and memory/storage products. Read More...

Fully integrated ETSI category 1 transceiver cuts 50% from cost and size

The CC1125 sub-1 GHz RF transceiver is a single-chip solution for wireless social alarms and ultra narrowband applications Read More...

>> SEE ALL

Teardown: The power inverter - from sunlight to power grid

This teardown of a solar inverter card traces the path of harvested DC power from the photovoltaic panel, through boost conversion, power inverter and massive filtering of the created AC power signal required by the power grid. Surrounded by monitoring and microcontroller magic along with safety standard adherence, we uncover the mysteries of solar energy harvesting electronics. Read More...

Integration amassed: analyzing a NAS

This hands-on project showcases the second generation of Western Digital's My Book World Edition NAS (network-attached storage) device, so named because it is potentially accessible by a user from anywhere in the world. Read More...

One sensor does the work of many

The single-array camera captures images that conventionally require an array of sensors. Read More...

Inside the Schick Hydro microcontroller-powered wet razor

Though the shaving experience may be overrated, a look inside the Schick Hydro reveals another unexpected application for microcontrollers—in this case a less-than-$1 PIC10F222 from Microchip. Read More...

Artificial cochlea: an example of structural processing

Prying Eyes: A MEMS-based artificial cochlea mimics the real thing in form and function. Read More...

TV peripheral encompasses superset processor

Prying Eyes looks inside the Delkin eFilm Picturevision, which enables the playback of audio, still-image, and video files on a variety of memory-card formats. Read More...

Teardown: The nuances of variable-frequency drives

Get an inside view of induction-motor control by varying frequency using PWM. Read More...

>> SEE ALL

MBIST verification: Best practices & challenges

Verification of functioning MBIST is an essential part in any SoC design cycle. Read More...

Challenges in LBIST validation for high reliability SoCs

The challenges of developing LBIST tester patterns for production, and ways of creating such patterns efficiently. Read More...

CDC verification of billion-gate SoCs

This article describes three different clock domain crossing (CDC) verification methodologies and how they can best be used in verifying SoCs being designed today. Read More...

Reduce SoC verification time through reuse in pre-silicon validation

This paper demonstrates a methodology to bridge the gap between SoC verification and pre-silicon validation and significantly reduce the debug effort and run-time of the verification sequences. Read More...

Pitfalls of state-transition clock gating

Blindly applying clock gating can result in the exact opposite of the desired effect. Read More...

A robust scan insertion methodology

Designers face multiple challenges in stitching the flops in SoCs to enable robust scan across all process voltage temperature corners. Read More...

JESD204B Subclasses (part 2): Subclass 1 vs. 2, System Considerations

Part 2 of the series takes a closer look at the differences between subclass 1 and subclass 2. In particular, we will look at the challenges to meeting the deterministic latency related timing requirements, device clock speed limitations in subclass 2, and guidelines on which subclass is best for a given system application. Read More...

Enhanced timing closure using latches

Latches are generally used in scan timing paths to provide robustness with respect to variations. Theoretically, latches can also be inserted in functional paths provided certain design conditions are ensured. Read More...

JESD204B Subclasses (part 1): Intro and Deterministic Latency

The intent of this “mini-tutorial” is to clarify the operational distinctions between the three JESD204B subclasses, and to provide the reader with a working knowledge on the implementation of their individual deterministic latency functionality. Read More...

Efficiency and memory footprint of Xilkernel for the Microblaze soft processor

The use of a real-time multitasking kernel simplifies the design process of embedded software, but the kernel requires some portion of system's resources. This paper describes results of research work performed to determine overheads incurred by Xilkernel, a real-time multitasking kernel developed by Xilinx. Read More...

Get smarter about production outlier removal

Part average testing is getting an upgrade that can help reduce yield losses because of device outliers without sacrificing quality. Get ready for PAT 2.0. Read More...

Logical chain-based clock implementation

A solution restrategizes timing optimization to tackle clocks and data logic concurrently. Read More...

Increasing observability of activity-based gating circuits

Adding XOR-based gates into the design has shown significant power saving in the SoC clock networks but requires methods to insert this circuitry while reducing the area and timing impact as well as boosting coverage of the design. Read More...

Novel low-power high-gain CMOS LNA for UWB receivers

This paper presents a highly linear low power and high gain CMOS common-gate LNA for UWB receivers. The proposed LNA uses current-reuse, forward-body biasing, and shunt-series peaking techniques. Read More...

CMOS 3-11GHz UWB LNA employs current-reuse

An ultra-wideband LNA utilizing current-reuse configuration is presented in this paper. With the current-reuse configuration at the input stage, the broadband input matching network has good reflected coefficient, and the power dissipation of the whole circuit is minimized. Read More...

Hierarchical timing analysis: Pros, cons, and a new approach

Cadence's Ruben Molina looks at the pros and cons of different hierarchical timing analysis approaches, as well as options for avoiding tradeoffs, including the latest Tempus tool. Read More...

Pin multiplexing considerations for a multi-million gate device

Look at the considerations for designing pin muxing in a large SoC. Read More...

Performance optimization using smart memory controllers, Part 1

In this article, we explain how a smart memory controller can improve the performance of a system. We discuss various issues in an SoC and describe features of a smart memory controller that can be configured to mitigate these issues. Read More...

Automate current measurements when characterizing SoCs

Save time and produce accurate, repeatable results by adding a multiplexer and running tests under computer control. Read More...

Basic principles of MEMS microphones

The application of MEMS (Micro Electro-Mechanical Systems) technology to microphones has led to the development of small microphones with very high performance. Read More...

>> SEE ALL

Design clock controllers for hierarchical test

Get the most out of hierarchical test by adding an on-chip clock controller. Read More...

A comparison of space-grade FPGAs - Part 2

For the latest, deep-submicron, space-grade FPGAs operating at higher frequencies with lower voltages and increased logic densities, SETs can dominate the soft-error rate. Read More...

DAC2014 Verification view

A look at the hustle, bustle, and acquisitions happening around DAC, with an eye to verification. Read More...

Spare cell leakage minimization in physical design, part 2 of 2

Pay attention to small details to reap power savings through leakage reduction. Read More...

Spare cell leakage minimization in physical design, part 1 of 2

Pay attention to small details to reap power savings through leakage reduction. Read More...

Analog Rails

I witnessed a designer take a 13 MHz VCO from a 250 nm design to a 40 nm design with no CAD setup and Electro-Migration (EM) taken into account. Read More...

SDC: WTH?

Is SDC crazy, or am I? How do you specify your FPGA timing? Read More...

Book: Constraining Designs for Synthesis and Timing Analysis

Book review and excerpt for the book: Constraining Designs for Synthesis and Timing Analysis: A practical guide to Synopsys Design Constraints Read More...

Remembrance of chips past

A look at some ICs from a kinder, simpler time. Read More...

Gone but Not Forgotten

Electronics companies get swallowed by other electronics companies. Read More...

BCD Rate Multiplier

A BCD coded rate multiplier can be a nice way to derive a signal whose frequency is settable to an input frequency multiplied by 0.1, 0.2 and so forth to 0.9 of the input frequency, but the periodicity of the rate multiplier output can be inconvenient. Read More...

A comparison of space-grade FPGAs - Part 1

FPGAs are increasingly being used in almost every spacecraft sub-system and designers now have a choice of process technologies and diverse fabrics. Which one is right for your mission? Read More...

DAC Vision from Wally Rhines

Mentor's Wally Rhines took the stage at DAC and spoke on opportunities in EDA and the coming end of Moore’s Law. When Moore’s Law makes it difficult to cost effectively shrink in the X-Y plane, we grow in the third dimension. Read More...

DAC Vision from Aart de Geus

We have reached the tipping point in the 50 year techonomic push-pull cycle. It is no longer just about costs but about value and impact… Read More...

An infographic history of cleanrooms

A quick look at the inventor and history of cleanrooms. Read More...

>> SEE ALL

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