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IC Design

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Suzanne Deffree
Editor
Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, related semiconductor manufacturing, and the design methodologies other IC designers are using to become successful.
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Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The traditional waterfall approach of SoC implementation can no longer guarantee a predictable schedule and reliable silicon. Upfront and thorough analysis, in every aspect of SoC development, is needed for today's SoC designs. Read More...

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Design for manufacturing and yield

Without increasingly sophisticated software, manufacturing at 28 nm has become highly problematic and yields uneconomically low. What can be done to enable this and smaller nodes to reach the desired yields? Read More...

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How FPGAs and multicore CPUs are changing embedded design

This article provides an overview of how the combination of FPGAs, multicore CPUs, and graphical programming environments such as the company’s LabVIEW are changing the nature of embedded systems design. Read More...

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SoC FPGAs combine performance and flexibility

Embedded-system architectures built on a combination of MCUs and FPGAs offer the kind of adaptability increasingly required to support changing demand for greater functionality across diverse applications. Read More...

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Book review: An ASIC Low Power Primer

Need to know about standards associated with low-power design? This book covers the ones you are most likely to encounter with a step-by-step guide to low power design… Read More...

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DVCon to spotlight latest in mixed-signal design and verification

Whether you are working on extending your digital verification methodology to AMS or looking for ways to improve performance of your analog flow by leveraging digital verification techniques, this DVCon tutorial is a must see. Read More...

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Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond

To date, transistor scaling has continued in accordance with Moore's Law down to 32 nm. Now the semiconductor industry is starting to deploy new technologies to address performance and power efficiency challenges, largely relying on "fully-depleted" transistors for continued scaling and performance gains. Read More...

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FPGA debugging techniques to speed up pre-silicon validation

This paper talks about some debugging techniques for FPGAs that can be adopted to speed up the validation process while at the same time highlighting some of their constraints. Read More...

>> SEE ALL
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Postprocessing converts Spice to RF analyzer

Designers of RF and high-frequency products need a simulator that can predict noise figure at a given frequency, minimum noise figure, optimum reflection coefficient for noise, and noise resistance. Read More...

Microcontroller drives piezoelectric buzzer at high voltage

Drive the buzzer directly from the μC’s I/O pins. Read More...

Voltage inverter employs PWM

Use two diodes and two capacitors to generate a negative voltage. Read More...

Build a UWB pulse generator on an FPGA

Make pulses that reach twice an FPGA's clock frequency. Read More...

Active multiplexing saves inputs

Add an inverter to reduce current and diodes to route inputs to a microcontroller's inputs as needed. Read More...

Design provides single-port-to-dual-port SDRAM converter

Read and write operations won't interfere with each other. Read More...

Relay driver switches two relays with one pin

Logic 1, logic 0, and high-Z make for three possible states: forward, reverse, and off. Read More...

Compute a histogram in an FPGA with one clock

Use a histogram to analyze large amounts of data. Read More...

Decode a quadrature encoder in software

Use a microcontroller to decode signals without the need for a dedicated IC. Read More...

Perform hexadecimal-to-BCD conversion in firmware

Converting in firmware eliminates a conversion chip. Read More...

>> SEE ALL

EDN Hot 100 products of 2012: EDA/IP and memory/storage

This section of EDN's Hot 100 Products of 2012 includes design automation software and memory/storage products. Read More...

Fully integrated ETSI category 1 transceiver cuts 50% from cost and size

The CC1125 sub-1 GHz RF transceiver is a single-chip solution for wireless social alarms and ultra narrowband applications Read More...

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Noise-cancelling ICs improve wireless headset audio quality

The AS3421, AS3422 single-chip ANC solutions feature an integrated speaker driver optimized for Bluetooth-enabled headset SoCs. Read More...

Voltage detector combines 0.58V reference and resettable latched comparator

The TS12001 voltage detector by Touchstone Semiconductor operates from a single 0.65V to 2.5V power supply and consumes less than 1μA total supply current. Read More...

Unified software environment makes engineers efficient

DIAdem 2012 is a single, unified software environment that makes engineers more efficient when locating, inspecting, visualizing, analyzing and reporting on data. Read More...

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Detection and configuration switch IC enriches audio headset experience

The TS3A225E audio headset detection and configuration switch IC enables universal headset support for audio apps in a single chip. Read More...

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Op amp, comparator and reference IC combo cuts power 10x

The TS12011 and TS12012 are 1.2μW op amp, comparator and voltage reference in one IC. Read More...

APM8669x processors enable domain protection for advanced system partitioning

The Black Mamba APM8669x is the highest performing member of the PacketPro2 family of multicore processors. Read More...

First silicon of Virtex-7 heterogeneous 3D FPGA ships

The Virtex-7 H580T, the first heterogeneous 3D FPGA is now shipping to key customers. Read More...

Google TV Devices with Vivante GPU Cores Ready for Android Jelly Bean Update

Read More...

>> SEE ALL
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Teardown: The power inverter - from sunlight to power grid

This teardown of a solar inverter card traces the path of harvested DC power from the photovoltaic panel, through boost conversion, power inverter and massive filtering of the created AC power signal required by the power grid. Surrounded by monitoring and microcontroller magic along with safety standard adherence, we uncover the mysteries of solar energy harvesting electronics. Read More...

Integration amassed: analyzing a NAS

This hands-on project showcases the second generation of Western Digital's My Book World Edition NAS (network-attached storage) device, so named because it is potentially accessible by a user from anywhere in the world. Read More...

One sensor does the work of many

The single-array camera captures images that conventionally require an array of sensors. Read More...

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Inside the Schick Hydro microcontroller-powered wet razor

Though the shaving experience may be overrated, a look inside the Schick Hydro reveals another unexpected application for microcontrollers—in this case a less-than-$1 PIC10F222 from Microchip. Read More...

Artificial cochlea: an example of structural processing

Prying Eyes: A MEMS-based artificial cochlea mimics the real thing in form and function. Read More...

TV peripheral encompasses superset processor

Prying Eyes looks inside the Delkin eFilm Picturevision, which enables the playback of audio, still-image, and video files on a variety of memory-card formats. Read More...

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Teardown: The nuances of variable-frequency drives

Get an inside view of induction-motor control by varying frequency using PWM. Read More...

>> SEE ALL
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Design for manufacturing and yield

Without increasingly sophisticated software, manufacturing at 28 nm has become highly problematic and yields uneconomically low. What can be done to enable this and smaller nodes to reach the desired yields? Read More...

image

Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The traditional waterfall approach of SoC implementation can no longer guarantee a predictable schedule and reliable silicon. Upfront and thorough analysis, in every aspect of SoC development, is needed for today's SoC designs. Read More...

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Using 3rd party IP in ASIC/SoC design

This article outlines some of the best practices for using the 3rd Party IP ecosystem as well as some of the common challenges in integrating and using 3rd party IPs in today’s high-end ASIC/SoCs. Read More...

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An introduction to offloading CPUs to FPGAs: Hardware programming for software developers

Researchers from Poland explain how to move C code to an FPGA-base implementation in a course for software developers. Read More...

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FPGA debugging techniques to speed up pre-silicon validation

This paper talks about some debugging techniques for FPGAs that can be adopted to speed up the validation process while at the same time highlighting some of their constraints. Read More...

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The current differencing transconductance amplifier (CDTA)

This article outlines a design method for CDTA-based resistor-less current-mode full balanced nth-order leapfrog ladder filter is presented. Read More...

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Smart power hook-up methodology for memories on SoCs

Meeting IR drop requirements on an SoC can often be a challenging task. This paper discusses a new hook-up methodology for memories on SoCs that can significantly reduce the worst IR drop on SoCs and also lead to improved performance. Read More...

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Stars of DesignCon: Silicon Interposer Spurs 3-D Chip Stacks

Rambus will explain how the die-to-die connections maintain routing and signal integrity up to 20 GHz. Read More...

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Stars of DesignCon: Signal integrity in tricked-out, high-speed interconnects

"Behavioral modeling allows signal-integrity engineers to sidesteps the time-consuming and error-prone process of building physical models," says DesignCon session host John Dunn. Read More...

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DesignCon's 5 Toughest Tech Questions

FPGA or ASIC? What are the issues for 3-D interconnects? Inquiring tech minds want to know. Read More...

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ASK & ANSWER

Top-down analog

A few days ago, I made a [url=http://www.edn.com/blog/Practical_Chip_Design/41761-Top_down_analog_flows_Myth_or_reality_.phphttp://]posting Read more...

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ASK & ANSWER
DAC in decline
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ASK & ANSWER
Determining floating nodes and floating gates.
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ASK & ANSWER
Can setup time + hold time be equal to zero??
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