IC Design

Michael Dunn
Editor, Design Ideas, IC/FPGA, PCB, and Medical Design Centres
Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, related semiconductor manufacturing, and the design methodologies other IC designers are using to become successful.

Hierarchical floorplanning comes of age

GUI-driven hierarchical floorplanning capabilities make big improvements in quality, time-to-tapeout, and design costs. Read More...

Don’t over-constrain in formal property verification (FPV) flows

Constraints are needed for FPV since they ensure that only legal input values are used. Learn the most effective method to avoid over-constraining, which can lead to hidden bugs. Read More...

Power management can cause latchup in CMOS chips

Cycling power with inputs applied can blow up your design. Read More...

LTC Design Note: Robust high voltage Over-the-Top op-amps maintain high input impedance with inputs driven apart or when powered down

Learn how the innards of an “over-the-top” op-amp work (where inputs can be higher than V+), as well as related design considerations. Read More...

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Simplified kurtosis computation detects signal interference

The statistical kurtosis operation, reinterpreted and implemented on an FPGA for this Design Idea, can detect various forms of interference in RF and other signals. Read More...

NRZ to AMI converter uses single supply

Convert serial data to AMI format with this simple Design Idea. Read More...

Circuit gates pulse train without truncating

This Design Idea accomplishes asynchronous gating without the worry of shortened pulses. Read More...

Anti-symmetric FIR filter slashes resource use

An anti-symmetric FIR design with the same implementation advantage as a symmetric. Read More...

Monolithic PWM generator runs fast, minimizes silicon

This analog-based PWM generator Design Idea does away with amplifiers and comparators to minimize space and power. Read More...

Single-cycle logarithms & antilogs

Here are some very fast log (and antilog) blocks well-suited to FPGA implementation. Read More...

Build a UWB pulse generator on an FPGA

Make pulses that reach twice an FPGA's clock frequency. Read More...

SDRAM interface slashes pin count

Many designs need deep buffering but don't require ultrahigh-memory bandwidth. Examples include image and audio processing, as well as some deep-FIFO applications. These designs often use a singlex8 SDRAM device that connects to an FPGA or ASIC. This approach solves the buffering problem but also burns a lot of valuable pins, which can be as many as 27 for a single SDRAM device. Read More...

Differential amp has 6dB lower noise, twice the bandwidth

Differential/instrumentation amp topologies possess varying trade-offs. Here’s one that improves noise & BW at the expense of input resistance. Read More...

Design provides single-port-to-dual-port SDRAM converter

Read and write operations won't interfere with each other. Read More...

Compute a histogram in an FPGA with one clock

Use a histogram to analyze large amounts of data. Read More...

PRBS generator runs at 1.5 Gbps

FPGA and serializer generate fast sequences to test communications links. Read More...

VHDL program enables PCI-bus-arbiter core

A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters. Read More...

Postprocessing converts Spice to RF analyzer

Designers of RF and high-frequency products need a simulator that can predict noise figure at a given frequency, minimum noise figure, optimum reflection coefficient for noise, and noise resistance. Read More...

Decode a quadrature encoder in software

Use a microcontroller to decode signals without the need for a dedicated IC. Read More...

Capacitive touch switch uses CPLD

Using an Altera MAX IIZ CPLD, you can implement a touch-switch decoder with no external components. Read More...

Swapping bits improves performance of FPGA-PWM counter

A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC. Read More...

Active multiplexing saves inputs

Add an inverter to reduce current and diodes to route inputs to a microcontroller's inputs as needed. Read More...

Perform hexadecimal-to-BCD conversion in firmware

Converting in firmware eliminates a conversion chip. Read More...

Implement a simple digital-serial NRZ data-recovery algorithm in an FPGA

A shift register and some logic lets you recover embedded clocks from data streams. Read More...

ADC for programmable logic uses one capacitor

Use a capacitor's charging and discharging time to sense a user input. Read More...

Stepper-motor motion controller and driver fit into a CPLD/FPGA

A CPLD or FPGA can be a home for a stepper-motor motion controller and driver. Read More...

Implement a stepper-motor driver in a CPLD

Replace a hard-to-find stepper-motor-driver IC with a programmable-logic device. Read More...

Add a Schmitt-trigger function to CPLDs, FPGAs, and applications

For slow-slewing signals, hysteresis solves trigger problem. Read More...

Three-phase digital-signal generator sweeps frequency

Use a clock divider to sweep frequency by 20 kHz. Read More...

Microcontroller drives piezoelectric buzzer at high voltage

Drive the buzzer directly from the μC’s I/O pins. Read More...

Voltage inverter employs PWM

Use two diodes and two capacitors to generate a negative voltage. Read More...

Relay driver switches two relays with one pin

Logic 1, logic 0, and high-Z make for three possible states: forward, reverse, and off. Read More...

Acquire images with a sensor and a microcontroller

Program a microncontroller to process images. Read More...

Sense multiple pushbuttons using only two wires

A single IC produces a code that indicates which button is pressed. Read More...

Hardware watchdog timer accepts range of frequencies

A timer removes power from a circuit should a microcontroller fail to produce pulses. Read More...

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FPGA married to in-package DRAM

Stratix 10 DRAM bottleneck broken with co-packaged DRAM. Read More...

5nm test chip taped out by imec, Cadence

Imec and Cadence have completed the first tape out of a test chip to be built using a 5nm manufacturing process. Read More...

PicoZed SDR enables application-level design

Avnet’s PicoZed SDR system-on-module combines Analog Devices' AD9361 RF agile transceiver with a Xilinx Zynq-7035 all-programmable SoC. Read More...

Evaluation kit jumpstarts FPGA embedded design

Arty is a customizable evaluation kit from Avnet that allows developers to prototype low-power designs based on the Xilinx Artix-7 35T FPGA. Read More...

SmartFusion2 development kit comes with JTAG emulator

Based on a SoC FPGA with embedded security, Avnet’s SmartFusion2 KickStart kit enables the prototyping of low-power, high-security IoT designs. Read More...

FPGA IP cores enable flexible SoC design

Optimized for TSMC’s 28-nm process, Menta’s predefined off-the-shelf IP cores for complex SoC devices simplify post-production customization. Read More...

Knowm's memristors alive & shipping

True bidirectional memristors are now available for experimentation as well as integration onto CMOS chips, enabling machine learning and other breakthrough apps. Read More...

ClioSoft updates EDA management platform

Version 7.0 of ClioSoft’s SOS design data and enterprise IP management platform is up to 30 times faster than previous versions. Read More...

Toshiba launches 256-Gbit 48-layer 3-D NAND flash

Ready for sampling in September, Toshiba’s 48-layer BiCS flash memory stores 256 Gbits using a 3-D vertically stacked cell structure. Read More...

Boundary-scan viewer offers trace imaging

Version 8.2 of the ScanExpress boundary-scan tool suite from Corelis adds trace imaging using ODB++ netlist data. Read More...

Globalfoundries launches FD-SOI processes

Globalfoundries Inc. has announced that it is offering a 22nm FD-SOI manufacturing platform that can operate down to 0.4V. Read More...

Artix-7 FPGA drives PC/104 I/O board

The EMC2-7A I/O board from Sundance integrates a PCI Express x4 Gen2 interface and reprogrammable logic on a PC/104 form factor called OneBank. Read More...

Pushing emulation beyond functional tests

With the launch of its Veloce Power Application software, Mentor Graphics advocates for the emulation of large SoCs beyond the typical sets of functional tests. Read More...

Fine-grained power architecture eases SoC design

Mainstream SoC design teams can use the ICE-Grain (Instant Control of Energy) power architecture from Sonics to automate power-management schemes that employ finely grained SoC partitions for use in a myriad of energy-sensitive consumer, IoT, mobile, wearable, automotive, and set-top box applications. Read More...

RF SOI process design kit leverages PSP-SOI model

Targeting both advanced wireless and wired applications, pure-play 200-mm foundry Shanghai Huahong Grace Semiconductor Manufacturing (HHGrace) and Gildenblat Consulting, a semiconductor modeling service and consulting company, jointly announced a 0.2-µm RF SOI (silicon-on-insulator) PDK (process design kit) containing Gildenblat’s PSP-SOI model. Read More...

Quartus gets under-the-hood reboot

Altera has released a new engine for its Quartus II software to scale up with the increasing density of large FPGAs. Read More...

Online portal speeds ASIC quotation process

To facilitate and improve the turnaround time for ASIC quotations, Open-Silicon has created a web portal for customers to submit their system requirements. Read More...

Fast extraction tool maintains high accuracy

Calibre xACT, a parasitic extraction platform from Mentor Graphics, provides attofarad accuracy and the ability to handle multimillion-instance designs to address a wide range of analog, digital, custom, and RF extraction requirements, including 14-nm FinFET. Read More...

Two-channel SMU sources and sinks

The GS820 source-measure unit from Yokogawa is available in 18 V and 50 V models. Read More...

Quantum computer kit announced – Save over $10,000,000!

The most exciting announcement this editor has ever covered: Quantum computing for the masses. Read More...

Xpedition Package Integrator spans IC chip to package to PCB

Mentor's new Package Integrator allows co-design of chips, single- & multi-chip packaging, and PCB layout. Read More...

Innovus Implementation System claims up to 10× turnaround time reduction

Cadence's new Innovus Implementation System shows impressive speedups and PPA results. Read More...

GaN transistor boosts efficiency, power density

Transphorm is offering engineering samples of the TPH3205WS, a 600-V GaN transistor in a small 3-pin TO-247 package that delivers high-efficiency operation in 80 Plus Titanium-class power-supply and inverter applications up to 3 kW. Read More...

One-stop-shop from IC design to silicon tape out

CEA-Leti has launched the Silicon Impulse IC design competence centre, offering IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles. Read More...

Extensible processor IP offers up to 75% memory power and area savings

Xtensa LX6 and Xtensa 11 processors enable users to create innovative custom processor instruction sets with up to 25% less processor logic power consumption and up to 75% better local memory area and power efficiency. Read More...

Catapult 8 a major HLS upgrade

Calypto is calling Catapult 8 "third generation" high-level synthesis technology, and it supports both C++ and SystemC. Read More...

PXI module exercises and characterizes DIO channels

The GX5295 from Marvin Test Solutions lets you add 32 DIO channels with source/sink capabilities to an PXI instrument chassis. Read More...

FPGA boards under $100: Altera/Terasic DE0-Nano

A close look at the Cyclone IV-based $79 DE0-Nano FPGA devboard from Terasic. Read More...

EDN Hot 100 products of 2014: EDA Tools, IP & Memory/Storage

This section of EDN's Hot 100 Products of 2014 includes design automation tools and memory/storage products. Read More...

FPGAs said to be industry’s most secure

Microsemi's ultra secure SmartFusion2 SoC FPGAs and IGLOO2 FPGAs are claimed to have more advanced security features at the device, design and system levels than any other leading FPGA. Read More...

Tabula FPGA provides 100% observability

Tabula's DesignInsight technology has the potential to provide a step-function improvement in development time and cost. Read More...

100 GHz real-time oscilloscope arrives

Teledyne LeCroy ups the oscilloscope bandwidth ante with the announcement of the LabMaster 10-100Zi. Read More...

Verification IP for 3D memory structures

Cadence Design Systems has announced verification IP supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube, High Bandwidth Memory, and DDR4 3D Stacking. Read More...

Memory IP targets low power requirements

In order to reach the stringent low power requirements of LCD drivers and touch screen controllers, Dolphin Integration has introduced a foundry-sponsored Single port RAM for the UMC 110 nm embedded Flash process. Read More...

MAX10 broadens the FPGA field

Altera's MAX series has graduated from CPLD to FPGA, and sports some unique features. Read More...

Audio analyzer claims world's lowest noise

Audio Precision's APx555 bridges the gap between bench and production testing while providing -117 dB of THD+N. Read More...

Mil temp-qualified FPGAs in 20-nm

Mil temp-qualified Arria 10 FPGAs and SoCs will allow military customers to make early specification decisions in designing avionics, radar and other high reliability applications, Altera says. Read More...

Cadence unveils Protium FPGA-based SoC prototyping platform

Protium puts two to eight Virtex-7 FPGAs under the hood to help you prototype & test complex SoCs. Read More...

NVM IP offers 75% area reduction

The non-volatile memory IP meets stringent automotive Grade 0 temperature and AEC-Q100 quality requirements. Read More...

Quantus QRC tears through extractions

Cadence's update to QRC, Quantus QRC, makes full use of your expensive server hardware, and can speed through extraction five times faster. Read More...

FPGA boards under $100: Introduction

I’m kicking off a major series of hands-on reviews of sub-$100 FPGA boards, so hop on “board” as we start our exploration. Read More...

iPad app from NI runs accurate SPICE simulations

Multisim Touch simulates circuit designs anywhere, anytime, says National Instruments; students, hobbyists and engineers can use the iPad app to design and simulate circuits using high-fidelity SPICE simulation with results identical to the desktop. Read More...

Path Finder mates PCB, IC package, & system design

The Xpedition Path Finder suite provides a single environment that gives cross-domain design teams the ability to model every device/interface. Read More...

IP for PHY connection to Hybrid Memory Cube is certified Compliant

Semtech's Snowbush family of 28-nm Platform Physical Layer IP offers support for the Hybrid Memory Cube specification for ultra fast, next-generation memory. Read More...

Dual-mode Soft IP core supports UART and FIFO operation

Digital Core Design has announced its D16950 soft IP core, featuring functional compatibility with the OX16C950 and an ability to support serial transmission in UART and FIFO modes. Read More...

I2C device interface IP for FPGA requires no programming

Digital Core Design has created DI2CSB -- an I2C slave base IP Core that doesn't need to be programmed. Read More...

Cypress adds entry-level chips to mixed-signal programmables

Expanding the PSoC 4 architecture with entry-level PSoC 4000 devices, Cypress has configured a family of low-cost ARM Cortex-M0 cores integrated with the CapSense, capacitive sensing system. Read More...

LPDDR4 IP offers 3200 Mbps performance

Synopsys LPDDR4 IP offering includes DesignWare LPDDR4 multiPHY, Enhanced Universal DDR Memory Controller and verification IP as well as hardening and signal integrity services Read More...

Streamline DDRx interface design with TimingDesigner/Sigrity melding

DDR design, especially DDR4, needs all the help it can get. Read More...

Companion FPGA packs 85K LUTs in 10x10mm package

The ECP5 FPGA Family was specifically designed to focus on key fast growing and high-volume markets such as small-cells, microservers, broadband access, or industrial video. Read More...

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Teardown: Apple iPhone 6 Plus battery

A look at Apple's iPhone 6 battery helps nail down the one variable that determines manufacturing cost. Read More...

1969 Compucorp calculator teardown

A 1969 scientific calculator teardown. This one's got them newfangled ICs. Read More...

Teardown: 1966 Programmable scientific calculator

Look inside a mid-1960s programmable scientific calculator! Read More...

Integration amassed: analyzing a NAS

This hands-on project showcases the second generation of Western Digital's My Book World Edition NAS (network-attached storage) device, so named because it is potentially accessible by a user from anywhere in the world. Read More...

One sensor does the work of many

The single-array camera captures images that conventionally require an array of sensors. Read More...

Inside the Schick Hydro microcontroller-powered wet razor

Though the shaving experience may be overrated, a look inside the Schick Hydro reveals another unexpected application for microcontrollers—in this case a less-than-$1 PIC10F222 from Microchip. Read More...

Artificial cochlea: an example of structural processing

Prying Eyes: A MEMS-based artificial cochlea mimics the real thing in form and function. Read More...

TV peripheral encompasses superset processor

Prying Eyes looks inside the Delkin eFilm Picturevision, which enables the playback of audio, still-image, and video files on a variety of memory-card formats. Read More...

Teardown: The nuances of variable-frequency drives

Get an inside view of induction-motor control by varying frequency using PWM. Read More...

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Don’t over-constrain in formal property verification (FPV) flows

Constraints are needed for FPV since they ensure that only legal input values are used. Learn the most effective method to avoid over-constraining, which can lead to hidden bugs. Read More...

Measure a video ADC's differential gain and phase

Measuring these two parameters can help you avoid sending video errors that can become visible to viewers. Read More...

Global approach to timing margins and constraint definition for SoC design, Part 1

With the latest deep sub-micron technologies, System on Chip (SoC) design is becoming more and more troublesome Read More...

Level-shifter block sips power

Level-shifter blocks are found throughout most SoCs, but they generally consume excess static power. The circuit described here cuts that power by three orders of magnitude. Read More...

Secure updates for FPGA-based systems

Here are some things you can do to ensure a secure, reliable, and safe remote update to an FPGA-based embedded system. Read More...

Improving fault coverage for random-pattern-resistant designs

Tips & techniques for aiming your LBIST testing at maximum coverage. Read More...

The year of 3D memory

3D ICs have been around for a while, but now they’re getting real. Read More...

ADC SNR effects due to parasitics, mismatch, and noise

Understanding sources of ADC noise & error will help you to design them out of your IC. Read More...

SoC PDN challenges and solutions

Partitioning and low-power modes increase PDN complexity. Read about some of the challenges and solutions. Read More...

How formal verification saves time in digital IP design

Learn how you too can save 30% in verification time. Read More...

Parametrized parallelized AMS testbenches speed detailed analysis

A tool-based solution to AMS verification speeds SoC design. Read More...

Making virtual prototypes work – A case study

A case study and recommendations for developing virtual prototype models. Read More...

PSI5 silicon validation setup is easily enhanced

Available test equipment for PSI5 isn’t enough to fully validate a system, so here’s what else you need. Read More...

Best design practices for DFT

A mini-course on best practices for SoC DFT Read More...

Timing closure in multi-level partitioned SoCs

Multi-level partitioning of a design leads to improved productivity, but there are challenges to be faced. Read More...

Reuse UVM RTL verification tests for gate level simulation

Learn how to reuse RTL tests in gate-level simulation. Read More...

Post-silicon randomized functional testing finds corner-case problems

Directed functional verification tests are necessary with any new IC design, but adding randomized testing will likely uncover a few extra bugs. Read More...

Reducing IC power consumption: Low-power design techniques

An overview of IC design techniques for reducing power consumption. Read More...

Aspects of IC power dissipation

An overview of IC power dissipation mechanisms. Read More...

Digital predistortion improves data-acquisition performance

Engineers from Maxim Integrated explain how digital predistortion improves the distortion performance of a digital signal generator, which provides for better measurement of an ultra-low-distortion DAS. Read More...

3D chip/package/PCB co-design optimizes systems: Product how-to

Today’s complex and dense systems require a holistic design approach, from chip to PCB level. Read More...

Ensure closure with proper latch constraints

Latches have multiple uses, but care is required in their specification. Read More...

7 Steps to a Successful Analog ASIC

I’m willing to bet that there are tens of thousands of analog applications out there that would benefit financially from ASIC integration. So what’s the holdup? Based on my 40+ years in the Analog IC business, I can boil it down to one word. Misinformation. Read More...

Reduce TNS/WNS in synthesis with individual path algorithm

A technique to reduce TNS & WNS across a design without getting hung up on the worst offenders. Read More...

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Hierarchical floorplanning comes of age

GUI-driven hierarchical floorplanning capabilities make big improvements in quality, time-to-tapeout, and design costs. Read More...

Enable IoT ASIC Design Using Platforms

It may seem premature to be talking about ASICs for IoT designs, but the platform approach can make IoT ASICS practical. Read More...

2016 Predictions for mixed-signal IC design

Complex mixed-signal SoC verification requires a system-level view—encompassing chip, package, and board—to ensure high-quality chips for application areas like automotive and IoT. Read More...

Accurate memory models for all

Accurate memory models are fundamental to SoC verification. Read about what to look for in models, and what the author likes about his company’s offering. Read More...

DesignCon2016: Prepare for the PAM4 phase shift

The shift from baseband NRZ to PAM4 provides the opportunity to leap to the edge and DesignCon2016 will get you there. Read More...

Whither logic analyzers?

Many scopes today have logic inputs. Whatever happened to the dedicated logic analyzer? Read More...

Circuit Seed wants to be the "ARM" of analog

Circuit Seed wants companies to license their unique CMOS analog circuit blocks. Read More...

Analog IP verification guidelines

Expert designers share their checklists for analog IP/IC verification. Read More...

Introducing the world’s first 28nm semiconductor for space, part 2

The specification of Altera's COTS FPGA for space applications and its range of logic resources and innovative fabric design exceeds by several generations the speed, bandwidth, and power advantages of current space-grade ASIC technology. Read More...

Metal eFuse teardown

This article examines two electrically blown fuse structures (eFuse) used in metal gate logic processes. Read More...

Cell-aware test can be “Awarding”

The cell-aware test (CAT) approach enables a transistor-level, defect-based automatic test pattern generation that significantly reduces the defect rate of manufactured ICs. Read More...

Vote for best ARM-based product

The ARM TechCon Innovation Challenge has announced the finalists, and its your turn to choose the Reader’s Choice Winner. Read More...

Parasitic extraction for touchscreen designs

See how an extraction tool can be used to model & verify a much larger device than an IC. Read More...

Webinar Sept. 17: S-Parameters

A webinar presented by SiSoft looks at how to check your models for errors. Read More...

Speed compile/verification under Synopsys VCS

Reduce compile/verification times with the “PIP” technique here. Read More...

Inside GlobalFoundries' Fab 8

Giant fab rides emerging NY tech corridor. Read More...

Hardware emulator performance

Emulation performance – or its speed of execution – depends on the architecture of the emulation system and the type of deployment. Read More...

Dennis Monticelli’s parting comments for engineers

Fifteen years ago Dennis Monticelli was named as a National Semiconductor Fellow and just recently has retired from Texas Instruments Silicon Valley (Formerly National Semiconductor) on July 31, 2015. Read More...

Automated ECOs boost your design productivity

Fully- and semi-automated ECO handling improves IC design quality and speed, and takes a load off the designers. Read More...

Test Points are Trending

You can use EDT Test Points for at-speed test. Read More...

Interconnect (NoC) verification in SoC design: Part 3

A reusable SoC interconnect/NoC verification approach catches errors. Read More...

Cloud EDA & DAC 2015 wrap-up

A DAC 2015 product wrap-up, including more cloud-based EDA and advanced silicon enablement. Read More...

Interconnect (NoC) verification in SoC design: Part 2

Use a “socket” concept to decouple IP cores from SoC busses. Read More...

Power analysis has a new look

A combination of emulation and power analysis software streamlines power estimation of massive SoC designs. Read More...

Bioresorbable electronics cap off DAC 2015

Though the last day of DAC is a bit of a winding down, it started with a remarkable keynote. Read More...

FPGAs, cloud design, and meta-tools at DAC 2015

A big part of DAC is the product exhibition area, and trends this year included FPGA IP, cloud design, meta tools, and more. Read More...

Insecure radio links and the end of Moore's Law discussed at DAC 2015

This recap from DAC 2015, taking place this week in San Francisco, covers radio security, the end of Moore's Law, FinFETs, and more. Read More...

Google Smart Lens kicks off DAC 2015

This year's Design Automation Conference kicked off in San Francisco this week with a keynote on the Google Smart Lens, Apple Watch and quadcopter teardowns, and more. Read More...

DAC52 Cometh

DAC (the Design Automation Conference) is right around the corner, and I'm going. Here's a brief preview of what I expect to see, so chime in with suggestions. Read More...

DesignCon 2016 opens call for papers

It’s time to sharpen your virtual pencils and submit your ideas for next year’s DesignCon. If your work concerns signal integrity, power integrity, or the interference between the two in high-speed designs, then DesignCon is the conference for you to show your work and get the feedback of your peers. Read More...

VCS commands ease coverage efforts & speed simulation

By using certain functions and commands in SystemVerilog and the Synopsys VCS tool, one can reduce coverage closure effort as well as the resultant simulation time. Read More...

A SystemC-based UVM verification infrastructure

TVS has made a SystemC library to enable UVM verification to be performed using SystemC rather than System Verilog freely available. Read More...

ARM TechCon opens call for proposals

Proposals now being accepted for ARM TechCon 2015, which will take place November 10-12, 2015 Read More...

Kintex-7, SEU mitigation using an isolated-design flow, part 1

Replicating and isolating redundant logic blocks within an FPGA fabric offers the potential of fault-tolerant implementation, confining SEUs to a single module preventing their propagation. Read More...

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