ESC Con 2015

IC Design

Michael Dunn
Editor, Design Ideas, IC/FPGA, PCB, and Medical Design Centres
Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, related semiconductor manufacturing, and the design methodologies other IC designers are using to become successful.

Innovus Implementation System claims up to 10× turnaround time reduction

Cadence's new Innovus Implementation System shows impressive speedups and PPA results. Read More...

Improving analog design verification using UVM

Use UVM (universal verification methodology) to improve verification of AMS SoCs. Read More...

Instrumentation amp makes an accurate transimpedance amp too

The interesting topology in this Design Idea turns a monolithic in-amp into a good transimpedance amp for photodiode or similar applications. Read More...

LTE-A Release 12 transmitter architecture: analog integration

In part 2 of a series, Damian Anzaldo explains how LTE-Advanced Release-12 shapes eNode transmitter architecture, specifically in terms of the analog integration challenge. The article includes an example using a MAX5868 RF DAC transmitter from Maxim Integrated. Read More...

RTL coding architecture affects power estimation & analysis

Small changes in RTL architecture can lead to big changes in power consumption. Read More...

Handle SEUs with C-slow retiming

Using C-Slow Retiming to generate a time-redundant digital design results in significantly reduced area and less power consumption, as compared to traditional techniques. Read More...

Design compilation in hardware emulators

Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology used in the verification engine. Read More...

What’s stopping pre-silicon emulation from covering the last mile?

It has become essential to have a well-defined pre-silicon emulation platform, along with SoC verification, to find all design faults early in the cycle. Read More...

One-stop-shop from IC design to silicon tape out

CEA-Leti has launched the Silicon Impulse IC design competence centre, offering IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles. Read More...

FinFET impact on dynamic power

FinFET-aware design implementation and effective dynamic power control throughout the flow is critical to unleash the full potential of these 3D devices. Read More...

18 Views of ISSCC

The latest and greatest chip R&D from ISSCC. Read More...

NRZ to AMI converter uses single supply

Convert serial data to AMI format with this simple Design Idea. Read More...

Test Memories at-speed with a slow clock

You may think that testing memory with a low-speed clock would miss many errors, but that's not the case. Read More...

Time for multimedia SoCs to get their analog signals right

As more and more analog I/O gets integrated onto SoCs, make sure you properly understand A/V signal characteristics and processing methods. Read More...

Entering the era of 3D printed electronics

A new development in 3D printing and conductive inks make 3D printed electronics a reality that will revolutionize electronics manufacturing starting this year. Read More...

Interconnect (NoC) verification in SoC design

Use a “socket” concept to decouple IP cores from SoC busses. Read More...

Silicon debug challenges and guidelines

Guidelines for faster, more effective diagnosis during silicon debug. Read More...

Simple analog ASIC solves difficult thermal analysis problems

In a world where Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) are dominating every conceivable application, greater attention is being applied to their long term reliability. Read More...

Sequential clock gating maximizes power savings at IP level

Obtain significant power savings with no impact to the rest of the design flow. Read More...

Thermal Modeling of Large Embedded GaN Transistors

This paper highlights the recent thermal characterization and simulation work carried out on large area embedded GaN power transistors. Two types of embedded formats are characterized and compared. Read More...

>> SEE ALL

NRZ to AMI converter uses single supply

Convert serial data to AMI format with this simple Design Idea. Read More...

Circuit gates pulse train without truncating

This Design Idea accomplishes asynchronous gating without the worry of shortened pulses. Read More...

Anti-symmetric FIR filter slashes resource use

An anti-symmetric FIR design with the same implementation advantage as a symmetric. Read More...

Monolithic PWM generator runs fast, minimizes silicon

This analog-based PWM generator Design Idea does away with amplifiers and comparators to minimize space and power. Read More...

Single-cycle logarithms & antilogs

Here are some very fast log (and antilog) blocks well-suited to FPGA implementation. Read More...

Build a UWB pulse generator on an FPGA

Make pulses that reach twice an FPGA's clock frequency. Read More...

SDRAM interface slashes pin count

Many designs need deep buffering but don't require ultrahigh-memory bandwidth. Examples include image and audio processing, as well as some deep-FIFO applications. These designs often use a singlex8 SDRAM device that connects to an FPGA or ASIC. This approach solves the buffering problem but also burns a lot of valuable pins, which can be as many as 27 for a single SDRAM device. Read More...

Differential amp has 6dB lower noise, twice the bandwidth

Differential/instrumentation amp topologies possess varying trade-offs. Here’s one that improves noise & BW at the expense of input resistance. Read More...

Design provides single-port-to-dual-port SDRAM converter

Read and write operations won't interfere with each other. Read More...

Compute a histogram in an FPGA with one clock

Use a histogram to analyze large amounts of data. Read More...

PRBS generator runs at 1.5 Gbps

FPGA and serializer generate fast sequences to test communications links. Read More...

VHDL program enables PCI-bus-arbiter core

A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters. Read More...

Postprocessing converts Spice to RF analyzer

Designers of RF and high-frequency products need a simulator that can predict noise figure at a given frequency, minimum noise figure, optimum reflection coefficient for noise, and noise resistance. Read More...

Decode a quadrature encoder in software

Use a microcontroller to decode signals without the need for a dedicated IC. Read More...

Capacitive touch switch uses CPLD

Using an Altera MAX IIZ CPLD, you can implement a touch-switch decoder with no external components. Read More...

Swapping bits improves performance of FPGA-PWM counter

A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC. Read More...

Active multiplexing saves inputs

Add an inverter to reduce current and diodes to route inputs to a microcontroller's inputs as needed. Read More...

Perform hexadecimal-to-BCD conversion in firmware

Converting in firmware eliminates a conversion chip. Read More...

Implement a simple digital-serial NRZ data-recovery algorithm in an FPGA

A shift register and some logic lets you recover embedded clocks from data streams. Read More...

ADC for programmable logic uses one capacitor

Use a capacitor's charging and discharging time to sense a user input. Read More...

Stepper-motor motion controller and driver fit into a CPLD/FPGA

A CPLD or FPGA can be a home for a stepper-motor motion controller and driver. Read More...

Implement a stepper-motor driver in a CPLD

Replace a hard-to-find stepper-motor-driver IC with a programmable-logic device. Read More...

Add a Schmitt-trigger function to CPLDs, FPGAs, and applications

For slow-slewing signals, hysteresis solves trigger problem. Read More...

Three-phase digital-signal generator sweeps frequency

Use a clock divider to sweep frequency by 20 kHz. Read More...

>> SEE ALL

Innovus Implementation System claims up to 10× turnaround time reduction

Cadence's new Innovus Implementation System shows impressive speedups and PPA results. Read More...

GaN transistor boosts efficiency, power density

Transphorm is offering engineering samples of the TPH3205WS, a 600-V GaN transistor in a small 3-pin TO-247 package that delivers high-efficiency operation in 80 Plus Titanium-class power-supply and inverter applications up to 3 kW. Read More...

One-stop-shop from IC design to silicon tape out

CEA-Leti has launched the Silicon Impulse IC design competence centre, offering IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles. Read More...

Extensible processor IP offers up to 75% memory power and area savings

Xtensa LX6 and Xtensa 11 processors enable users to create innovative custom processor instruction sets with up to 25% less processor logic power consumption and up to 75% better local memory area and power efficiency. Read More...

Catapult 8 a major HLS upgrade

Calypto is calling Catapult 8 "third generation" high-level synthesis technology, and it supports both C++ and SystemC. Read More...

PXI module exercises and characterizes DIO channels

The GX5295 from Marvin Test Solutions lets you add 32 DIO channels with source/sink capabilities to an PXI instrument chassis. Read More...

FPGA boards under $100: Altera/Terasic DE0-Nano

A close look at the Cyclone IV-based $79 DE0-Nano FPGA devboard from Terasic. Read More...

EDN Hot 100 products of 2014: EDA Tools, IP & Memory/Storage

This section of EDN's Hot 100 Products of 2014 includes design automation tools and memory/storage products. Read More...

FPGAs said to be industry’s most secure

Microsemi's ultra secure SmartFusion2 SoC FPGAs and IGLOO2 FPGAs are claimed to have more advanced security features at the device, design and system levels than any other leading FPGA. Read More...

Tabula FPGA provides 100% observability

Tabula's DesignInsight technology has the potential to provide a step-function improvement in development time and cost. Read More...

100 GHz real-time oscilloscope arrives

Teledyne LeCroy ups the oscilloscope bandwidth ante with the announcement of the LabMaster 10-100Zi. Read More...

Verification IP for 3D memory structures

Cadence Design Systems has announced verification IP supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube, High Bandwidth Memory, and DDR4 3D Stacking. Read More...

Memory IP targets low power requirements

In order to reach the stringent low power requirements of LCD drivers and touch screen controllers, Dolphin Integration has introduced a foundry-sponsored Single port RAM for the UMC 110 nm embedded Flash process. Read More...

MAX10 broadens the FPGA field

Altera's MAX series has graduated from CPLD to FPGA, and sports some unique features. Read More...

Audio analyzer claims world's lowest noise

Audio Precision's APx555 bridges the gap between bench and production testing while providing -117 dB of THD+N. Read More...

Mil temp-qualified FPGAs in 20-nm

Mil temp-qualified Arria 10 FPGAs and SoCs will allow military customers to make early specification decisions in designing avionics, radar and other high reliability applications, Altera says. Read More...

Cadence unveils Protium FPGA-based SoC prototyping platform

Protium puts two to eight Virtex-7 FPGAs under the hood to help you prototype & test complex SoCs. Read More...

NVM IP offers 75% area reduction

The non-volatile memory IP meets stringent automotive Grade 0 temperature and AEC-Q100 quality requirements. Read More...

Quantus QRC tears through extractions

Cadence's update to QRC, Quantus QRC, makes full use of your expensive server hardware, and can speed through extraction five times faster. Read More...

FPGA boards under $100: Introduction

I’m kicking off a major series of hands-on reviews of sub-$100 FPGA boards, so hop on “board” as we start our exploration. Read More...

iPad app from NI runs accurate SPICE simulations

Multisim Touch simulates circuit designs anywhere, anytime, says National Instruments; students, hobbyists and engineers can use the iPad app to design and simulate circuits using high-fidelity SPICE simulation with results identical to the desktop. Read More...

Path Finder mates PCB, IC package, & system design

The Xpedition Path Finder suite provides a single environment that gives cross-domain design teams the ability to model every device/interface. Read More...

IP for PHY connection to Hybrid Memory Cube is certified Compliant

Semtech's Snowbush family of 28-nm Platform Physical Layer IP offers support for the Hybrid Memory Cube specification for ultra fast, next-generation memory. Read More...

Dual-mode Soft IP core supports UART and FIFO operation

Digital Core Design has announced its D16950 soft IP core, featuring functional compatibility with the OX16C950 and an ability to support serial transmission in UART and FIFO modes. Read More...

I2C device interface IP for FPGA requires no programming

Digital Core Design has created DI2CSB -- an I2C slave base IP Core that doesn't need to be programmed. Read More...

Cypress adds entry-level chips to mixed-signal programmables

Expanding the PSoC 4 architecture with entry-level PSoC 4000 devices, Cypress has configured a family of low-cost ARM Cortex-M0 cores integrated with the CapSense, capacitive sensing system. Read More...

LPDDR4 IP offers 3200 Mbps performance

Synopsys LPDDR4 IP offering includes DesignWare LPDDR4 multiPHY, Enhanced Universal DDR Memory Controller and verification IP as well as hardening and signal integrity services Read More...

Streamline DDRx interface design with TimingDesigner/Sigrity melding

DDR design, especially DDR4, needs all the help it can get. Read More...

Companion FPGA packs 85K LUTs in 10x10mm package

The ECP5 FPGA Family was specifically designed to focus on key fast growing and high-volume markets such as small-cells, microservers, broadband access, or industrial video. Read More...

Software library enables FPGA-based drive control

The XSG AC Motor Control Library from software tool vendor dSpace speeds the development of Xilinx FPGA-based motor control designs. Read More...

Debugger teams with ARM’s System Trace Macrocell

Enhancements to Asset InterTech’s Arium hardware-assisted SourcePoint debugger optimize the processing of ARM’s System Trace Macrocell (STM), which provides developers of multicore, multithreaded SoCs a system-level perspective of trace data. Read More...

Software eases interconnect analysis of ARM-based SoCs

Interconnect Workbench from Cadence provides interconnect performance analysis and verification of SoC (system-on-chip) devices incorporating ARM CoreLink CCI-400, NIC-400, NIC-301, and ADB-400 system intellectual property (IP). Read More...

Hypervisor delivers security for multicore processors, enables multi-OS consolidation

Mentor Graphics has introduced an embedded hypervisor product for in-vehicle infotainment systems, telematics, advanced driver assistance systems, and instrumentation. Read More...

FastSPICE simulator offers up to 10X faster throughput

Cadence has introduced Spectre XPS (eXtensive Partitioning Simulator), featuring a breakthrough partitioning technology, that enables higher capacity and faster simulation while requiring two to three times less system memory. Read More...

Synopsys aims at TVs with ARC-based Dolby MS11 decoder

Synopsys' DesignWare IP for ARC Audio Processors has been augmented with support for Dolby Laboratories' Multistream Decoding, expanding the portfolio of ARC audio codecs. Read More...

System builder design tool targets ARM-based SmartFusion2 SoC FPGAs

Microsemi's System Builder is a new design tool within the Libero System-on-Chip (SoC) Design Environment version 11.0 and is specifically targeted at accelerating customer definition and implementation of ARM-based systems using SmartFusion2 SoC FPGAs. Read More...

FPGA/SoC families debut with performance boost, power reduction

Altera has announced its Generation 10 family comprising its Arria 10 and Stratix 10 series of FPGAs and SoCs. Read More...

Requirements lifecycle management tool targets safety-critical FPGA and ASIC design

Aldec's Spec-TRACER is a requirements lifecycle management solution for use in safety-critical industries in which rigorous certification standards exist; such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear. Read More...

Virtex 7-based FPGA module targets multi FPGA prototyping

Pro Design has added the proFPGA V7 mini FPGA module to its family of FPGA based prototyping solutions. Read More...

EDN Hot 100 products of 2012: EDA/IP and memory/storage

This section of EDN's Hot 100 Products of 2012 includes design automation software and memory/storage products. Read More...

Compact recorder boasts wide instantaneous bandwidth

Supplied in a rugged portable or standard rack enclosure, the dual-channel IQC5000B RF record and playback system from X-Com Systems accommodates wide signal bandwidths for use in electronic warfare, interference analysis, spectrum monitoring, and surveillance. Read More...

Service speeds industrial IoT development

Industrial IoT developers can get a helping hand through FastTrax. Read More...

Front-end modules target 4G LTE smart phones and tablets

RF Flex integrated front-end transmit and power-amplifier modules from Qorvo provide regional customization to improve the performance and simplify the design of 4G LTE smart phones and tablets, with the first products in the series aimed at the growing mid-tier segment in China. Read More...

PCB design tool links Altium & SolidWorks

PCBWorks is a PCB design tool created by Altium to enhance workflow collaboration between electrical and mechanical designers. Read More...

15-GHz RF detector delivers fast response time

Able to withstand 125°C operating environments, the LTC5564H Schottky peak power detector from Linear Technology operates over a frequency range of 600 MHz to 15 GHz with a detection response time of 7 ns from a pulsed RF signal. Read More...

ams, ST team for NFC reference design

An NFC (near-field communication) system reference design combines the AS39230 analog front-end IC with boostedNFC technology from ams and the ST21NFCC NFC controller and ST33G1M2 secure microcontroller from STMicroelectronics to enable secure, contactless transactions using mobile and wearable devices. Read More...

RF SOI switch operates up to 40 GHz

A high-performance alternative to GaAs-based switches, the PE42524 SPDT RF switch is manufactured on Peregrine Semiconductor’s UltraCMOS process—a patented variation of SOI (silicon on insulator) technology on a sapphire substrate—and one of the industry’s first RF SOI switches to operate up to 40 GHz. Read More...

Wi-Fi equipped 32-bit Arduino board streamlines cloud-powered embedded app development

Digilent's chipKIT WiFire board is an awesome little beastie. Powered by Microchip's powerful 32-bit 200 MHz MCU, the Wi-Fi equipped Arduino-compatible platform has been paired with Imagination Technologies' Flow Cloud service development tools in an effort to make creating cloud-powered embedded applications practical for the average developer. Read More...

RF switch preserves signal integrity from DC to 8 GHz

A reliable alternative to problematic mechanical relays and MEMS switches, the PE42020 UltraCMOS integrated RF switch from Peregrine Semiconductor operates from 0 Hz to 8 GHz, while offering high power handling and good RF performance and linearity. Read More...

Chip enables smart car access in wearables

A single-chip device from NXP Semiconductors, the NCF29A1 combines passive keyless entry with an RF transmitter for remote control and an immobilizer in a 32-pin QFN package to create car-access solutions that can be embedded in smart phones, smart watches, and car keys. Read More...

>> SEE ALL

1969 Compucorp calculator teardown

A 1969 scientific calculator teardown. This one's got them newfangled ICs. Read More...

Teardown: 1966 Programmable scientific calculator

Look inside a mid-1960s programmable scientific calculator! Read More...

Integration amassed: analyzing a NAS

This hands-on project showcases the second generation of Western Digital's My Book World Edition NAS (network-attached storage) device, so named because it is potentially accessible by a user from anywhere in the world. Read More...

One sensor does the work of many

The single-array camera captures images that conventionally require an array of sensors. Read More...

Inside the Schick Hydro microcontroller-powered wet razor

Though the shaving experience may be overrated, a look inside the Schick Hydro reveals another unexpected application for microcontrollers—in this case a less-than-$1 PIC10F222 from Microchip. Read More...

Artificial cochlea: an example of structural processing

Prying Eyes: A MEMS-based artificial cochlea mimics the real thing in form and function. Read More...

TV peripheral encompasses superset processor

Prying Eyes looks inside the Delkin eFilm Picturevision, which enables the playback of audio, still-image, and video files on a variety of memory-card formats. Read More...

Teardown: The nuances of variable-frequency drives

Get an inside view of induction-motor control by varying frequency using PWM. Read More...

>> SEE ALL

LTE-A Release 12 transmitter architecture: analog integration

In part 2 of a series, Damian Anzaldo explains how LTE-Advanced Release-12 shapes eNode transmitter architecture, specifically in terms of the analog integration challenge. The article includes an example using a MAX5868 RF DAC transmitter from Maxim Integrated. Read More...

RTL coding architecture affects power estimation & analysis

Small changes in RTL architecture can lead to big changes in power consumption. Read More...

Handle SEUs with C-slow retiming

Using C-Slow Retiming to generate a time-redundant digital design results in significantly reduced area and less power consumption, as compared to traditional techniques. Read More...

What’s stopping pre-silicon emulation from covering the last mile?

It has become essential to have a well-defined pre-silicon emulation platform, along with SoC verification, to find all design faults early in the cycle. Read More...

Test Memories at-speed with a slow clock

You may think that testing memory with a low-speed clock would miss many errors, but that's not the case. Read More...

Time for multimedia SoCs to get their analog signals right

As more and more analog I/O gets integrated onto SoCs, make sure you properly understand A/V signal characteristics and processing methods. Read More...

Interconnect (NoC) verification in SoC design

Use a “socket” concept to decouple IP cores from SoC busses. Read More...

Simple analog ASIC solves difficult thermal analysis problems

In a world where Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) are dominating every conceivable application, greater attention is being applied to their long term reliability. Read More...

Sequential clock gating maximizes power savings at IP level

Obtain significant power savings with no impact to the rest of the design flow. Read More...

Thermal Modeling of Large Embedded GaN Transistors

This paper highlights the recent thermal characterization and simulation work carried out on large area embedded GaN power transistors. Two types of embedded formats are characterized and compared. Read More...

Image compression overview

Lossy image compression is ubiquitous. Learn some of the key concepts here. Read More...

Comparing Verilog-AMS vs. SPICE view usage for robust AMS Verification of Power Management Controller and Mode Transition

The importance of a high level of power efficiency also means that several modes like Standby, Low power, Reduced Clock Mode, etc. also need to be supported. Read More...

Timing challenges for serial flash interface

This paper not only covers the timing challenges in every mode (SDR, DDR, DQS) of external serial NOR flashes, but also talks about the specific timing requirements to be used in closing the static timing in all these modes, independent of flash vendor. Read More...

Stressing of redundant memory bits during burn-in test

Uniformly stress-test memory during burn-in, including the spare cells. Read More...

Implement a VXLAN-based network into an SoC

Here’s how to eliminate bottlenecks in hyperscale cloud datacenter SoCs with VXLAN-based networks over 10G Ethernet IP Read More...

Model package parasitics with IBIS

Modeling parasitic capacitance and inductance lets you predict system performance. Read More...

In memory of John Haslet Hall, Intersil co-founder

Quite un-noticed by the electronics industry and without much tribute, John H. Hall passed away on October 30, 2014. Read More...

Sub-Threshold Design - A Revolutionary Approach to Eliminating Power

While reducing energy consumption is critically important throughout the electronics industry, the question is: how should that goal be achieved? Ambiq Micro’s approach moves beyond the incremental improvements that other semiconductor companies have taken and makes revolutionary advances through a unique approach to the problem: sub-threshold circuit design. Read More...

SoC clock monitoring issues: Scenarios and root cause analysis

A close look at clock-monitoring units for safety-critical designs. Read More...

Prevent quality mishaps using an automated SoC register access & reset verification

Don’t forget to test the little things in a new SoC design. Read More...

>> SEE ALL

Improving analog design verification using UVM

Use UVM (universal verification methodology) to improve verification of AMS SoCs. Read More...

FinFET impact on dynamic power

FinFET-aware design implementation and effective dynamic power control throughout the flow is critical to unleash the full potential of these 3D devices. Read More...

18 Views of ISSCC

The latest and greatest chip R&D from ISSCC. Read More...

Security needs more than checklist compliance

Following a checklist of requirements is only a start for designing security into electronics products. Read More...

Entering the era of 3D printed electronics

A new development in 3D printing and conductive inks make 3D printed electronics a reality that will revolutionize electronics manufacturing starting this year. Read More...

Silicon debug challenges and guidelines

Guidelines for faster, more effective diagnosis during silicon debug. Read More...

A powerful power integrity workshop

A DesignCon'15 tutorial covers power integrity & PDN design in-depth. Read More...

Moore's Law extends to cover human progress

Moore's Law comes from the way people work and we can derive Moore’s-like laws for almost any developing technology or human endeavor. Read More...

Advanced fault models in small-scale CMOS technology nodes

Conventional tests fail at advanced CMOS nodes. More advanced fault models must be considered. Read More...

No glitter, games, or gimmicks, please

Trade show exhibits should stick to the technical and spare us the distractions. Read More...

Guidelines improve test quality in advanced CMOS nodes

IC test strategies to avoid false positives and improve yields. Read More...

Get a taste of SPICE at DesignCon

Every engineer needs easy access to a SPICE simulator tool. Get introduced to possibly the world's best SPICE tool at a DesignCon speed training event. Read More...

Vote for the Engineer of the Year

DesignCon2015 has announced the finalists for the Engineer of the Year Award (sponsored by National Instruments). The award includes a $10,000 grant that will be given out at DesignCon. Read More...

Design for test boot camp, Part 4: Built-in self-test

Built-in self-test is more than just test. It includes repair of failed circuits. Read More...

Clock monitors in SoC verification

Save time verifying clocks in complex IC designs. Read More...

Low power design – A case for RTL power analysis II

A look at the inaccuracies in RTL power analysis. Read More...

Design for test boot camp, part 2: Test compression

Test compression adds a small amount of circuitry for test purposes and drastically reduces test time while maintaining test coverage. Read More...

Multiple clock domain SoCs: Verification techniques

The authors discuss their experiences and share hints for the tools they use to verify complex designs. Read More...

Multiple clock domain SoCs: Addressing structural defects

The einfochips authors continue their in-depth look at multiple-clock domain designs. Read More...

Use test data to diagnose failed memory

A technique called ESOE (Enhanced Stop on Error) enhances memory-controller circuits so the controller stores the targeted failure number internally and keeps track of when failures occur. Read More...

Low power design – A case for RTL power analysis

Measuring power use at the gate level can be accurate, but slow. Can we measure at the RTL? Read More...

Guard-bands reduce MOSFET failures in space, part 1

MOSFETs that go into spacecraft power modules to drive motors need to functions properly after exposure to radiation. Part 1 explains shy guard bands are needed for dice testing. Read More...

Synchronizer techniques for multi-clock domain SoCs & FPGAs

Go way beyond the simple two F-F synchronizer in this survey of techniques. Read More...

Managing power network integrity and voltage drop in design implementation

Voltage drop and electromigration are just two IC power issues that need to be addressed throughout the design flow. Read More...

Efficiently estimate & optimize leakage in SoCs

Here’s a CAD-driven technique proven to reduce leakage power. Read More...

>> SEE ALL

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