IC Design

Michael Dunn
Editor, Design Ideas, IC/FPGA, PCB, and Medical Design Centres
Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, related semiconductor manufacturing, and the design methodologies other IC designers are using to become successful.

Advanced PCB & die-mounting technologies combined for dimension shrinks

PCB design and manufacturing company AT&S has brought together a range of technology options for miniaturization on all interconnection layers, including embedded component packaging, HDI, & bare-die packaging. Read More...

Verification “escapes” leave bugs in silicon

Here’s practical advice to stop bugs from getting through, or “escaping”, verification. Read More...

Electrical engineering in the 1960s: The transistor changed everything

Everything we do today in electronics is based on the transistor, but it wasn't always that way. Here's how one engineer described what happened when transistors came along. Read More...

Resets in FPGA & ASIC control and data paths

Don’t take resets for granted in your design. Read More...

28nm was last node of Moore's Law

The industry is at a crossroads: some designs pursue scaling to 7nm while the majority stay on 28nm or older nodes. Read More...

19 Views of Hot Chips

The annual Hot Chips event reflected a semiconductor industry moving rapidly in multiple directions with a lot of energy pouring into machine learning, smarter cars and novel sensors. Read More...

Back-annotating DFM enhancements to place & route tools

By enabling back-annotation of DFM shapes and information to P&R, file translation can also help to reduce iterations and close timing while ensuring the optimized layout remains DRC-compliant. Read More...

ARM intrusive debugging for post-silicon SoC validation

Read about debugging options and examples for complex SoC designs. Read More...

What DFT history teaches us

An EDN article from 1988 shows the state of design for test at that time, now see how it has evolved. Read More...

Electromigration protection requires accurate interconnect modeling

Learn about electromigration and how to deal with it. Read More...

Source synchronous interface timing closure

Learn about different types of source-synchronous interface and their timing challenges. Read More...

Choosing a mobile-storage interface: eMMC or UFS

Consider the pros and cons of these evolving standards for your next SoC or system design. Read More...

The future of IC design

By 2076, 3D room-temperature, superconducting, quantum, neuromorphic, and photonic mixed-signal devices will be the common denominator for all integrated circuit designs. Read More...

FPGA constraints for the modern world: Product how-to

Writing design constraints can be onerous; tools can help. Read More...

Zero-mask-adder NVM vs. Embedded flash

A zero-mask-adder NVM solution for SoCs can be more economical than embedded flash. Read More...

Moving averager rejects noisy outlier values

Improve data-acquisition performance by implementing a smart filter in your FPGA, SoC, or code. Read More...

IC Debugging: Simulation vs. Lab validation

IC design verification has been the biggest challenge for decades now. Read how simulation fits in. Read More...

SoC Spec defines core interfaces

HSA version 1.1 defines IP block interfaces. Read More...

Synthesis platform aims to halve design time

Catapult decreases the hardware design time from design start to RTL verification closure by 50%, reports Mentor Graphics. Read More...

DAC 2016 in pictures

The buzz from the 53rd DAC in Austin. Read More...

Experiences with hardware emulation

The 2016 Mentor Graphics' User Group boasted five technical sessions focused on emulation. Read More...

10 Ways to program your FPGA

Go way beyond the Verilog/VHDL basics. Read More...

Use VUnits for assertions & functional coverage

VUnits help in the reduction of hundreds of lines of assertions and functional coverage to smaller pieces of code. Read More...

Understanding WGL scan data structures and some common issues

The way in which scan is handled within WGL files is often a source of confusion for engineers. Read More...

Proper oscilloscope setup yields correct ESD measurements

To get the right measurements of ESD pulses, you need to set trigger levels properly and use as much of the ADC as possible. Read More...

>> SEE ALL

Moving averager rejects noisy outlier values

Improve data-acquisition performance by implementing a smart filter in your FPGA, SoC, or code. Read More...

Control an FPGA bus without using the processor

A bit of added hardware lets FPGA engineers access peripherals without having to deal with the processor. Read More...

Simplified kurtosis computation detects signal interference

The statistical kurtosis operation, reinterpreted and implemented on an FPGA for this Design Idea, can detect various forms of interference in RF and other signals. Read More...

NRZ to AMI converter uses single supply

Convert serial data to AMI format with this simple Design Idea. Read More...

Circuit gates pulse train without truncating

This Design Idea accomplishes asynchronous gating without the worry of shortened pulses. Read More...

Anti-symmetric FIR filter slashes resource use

An anti-symmetric FIR design with the same implementation advantage as a symmetric. Read More...

Monolithic PWM generator runs fast, minimizes silicon

This analog-based PWM generator Design Idea does away with amplifiers and comparators to minimize space and power. Read More...

Single-cycle logarithms & antilogs

Here are some very fast log (and antilog) blocks well-suited to FPGA implementation. Read More...

Build a UWB pulse generator on an FPGA

Make pulses that reach twice an FPGA's clock frequency. Read More...

SDRAM interface slashes pin count

Many designs need deep buffering but don't require ultrahigh-memory bandwidth. Examples include image and audio processing, as well as some deep-FIFO applications. These designs often use a singlex8 SDRAM device that connects to an FPGA or ASIC. This approach solves the buffering problem but also burns a lot of valuable pins, which can be as many as 27 for a single SDRAM device. Read More...

Differential amp has 6dB lower noise, twice the bandwidth

Differential/instrumentation amp topologies possess varying trade-offs. Here’s one that improves noise & BW at the expense of input resistance. Read More...

Design provides single-port-to-dual-port SDRAM converter

Read and write operations won't interfere with each other. Read More...

Compute a histogram in an FPGA with one clock

Use a histogram to analyze large amounts of data. Read More...

PRBS generator runs at 1.5 Gbps

FPGA and serializer generate fast sequences to test communications links. Read More...

VHDL program enables PCI-bus-arbiter core

A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters. Read More...

Postprocessing converts Spice to RF analyzer

Designers of RF and high-frequency products need a simulator that can predict noise figure at a given frequency, minimum noise figure, optimum reflection coefficient for noise, and noise resistance. Read More...

Decode a quadrature encoder in software

Use a microcontroller to decode signals without the need for a dedicated IC. Read More...

Capacitive touch switch uses CPLD

Using an Altera MAX IIZ CPLD, you can implement a touch-switch decoder with no external components. Read More...

Swapping bits improves performance of FPGA-PWM counter

A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC. Read More...

Active multiplexing saves inputs

Add an inverter to reduce current and diodes to route inputs to a microcontroller's inputs as needed. Read More...

Perform hexadecimal-to-BCD conversion in firmware

Converting in firmware eliminates a conversion chip. Read More...

Implement a simple digital-serial NRZ data-recovery algorithm in an FPGA

A shift register and some logic lets you recover embedded clocks from data streams. Read More...

ADC for programmable logic uses one capacitor

Use a capacitor's charging and discharging time to sense a user input. Read More...

Stepper-motor motion controller and driver fit into a CPLD/FPGA

A CPLD or FPGA can be a home for a stepper-motor motion controller and driver. Read More...

Implement a stepper-motor driver in a CPLD

Replace a hard-to-find stepper-motor-driver IC with a programmable-logic device. Read More...

Add a Schmitt-trigger function to CPLDs, FPGAs, and applications

For slow-slewing signals, hysteresis solves trigger problem. Read More...

Three-phase digital-signal generator sweeps frequency

Use a clock divider to sweep frequency by 20 kHz. Read More...

Microcontroller drives piezoelectric buzzer at high voltage

Drive the buzzer directly from the μC’s I/O pins. Read More...

Voltage inverter employs PWM

Use two diodes and two capacitors to generate a negative voltage. Read More...

Relay driver switches two relays with one pin

Logic 1, logic 0, and high-Z make for three possible states: forward, reverse, and off. Read More...

Acquire images with a sensor and a microcontroller

Program a microncontroller to process images. Read More...

>> SEE ALL

Advanced PCB & die-mounting technologies combined for dimension shrinks

PCB design and manufacturing company AT&S has brought together a range of technology options for miniaturization on all interconnection layers, including embedded component packaging, HDI, & bare-die packaging. Read More...

Synthesis platform aims to halve design time

Catapult decreases the hardware design time from design start to RTL verification closure by 50%, reports Mentor Graphics. Read More...

BERT takes on 400 Gbps links

Keysight's M8040A bit-error-ratio tester is ready for today's high-speed link testing with enhancements for the next generation. Read More...

Design Recipes for FPGAs: Book review

Peter Wilson’s new book "Design Recipes for FPGAs" makes a great addition to the FPGA literature. Read More...

Quartus Prime boosts FPGA design productivity

Quartus Prime 16.0 speeds compilation, pin assignments, and clock planning. Read More...

FEI offers mid-range SEM

The Apreo SEM (scanning electron microscope) from FEI is capable of resolution down to 1.0 nm at 1 kV without the need for beam deceleration. Read More...

Mixed-signal glue chip incorporates I2C & state machine

Silego's GPAK 5 joins the company’s configurable mixed-signal ICs, with features such as an asynchronous state machine, zero static power, and I2C for on-the-fly reconfiguration. Read More...

Digital filter designer is graphical & intuitive

Version 3.0 of ASN Digital Filter Designer for IIR and FIR filter design offers an intuitive route to implementing digital filters that represents the first significant advance in this class of tools for many years. Read More...

Industrial SBC sports FPGA fabric

Sundance Multiprocessor Technology Ltd has integrated Xilinx’s new SDSoC development environment onto an SBC. Read More...

Memory chips cut power in connected devices

Adesto Technologies reports that its Moneta nonvolatile serial memories consume 50 to 100 times less power during read and write operations. Read More...

The fourth age of emulation

Mentor bring new capabilities to Veloce emulation, greatly enhancing its usefulness, speed, and repeatability. Read More...

ARM Cortex-R8 raises realtime performance

The ARM Cortex-R8 processor is expected to help chip designers double the performance of ARM-based modem and mass storage SoCs for example. Read More...

FPGA married to in-package DRAM

Stratix 10 DRAM bottleneck broken with co-packaged DRAM. Read More...

5nm test chip taped out by imec, Cadence

Imec and Cadence have completed the first tape out of a test chip to be built using a 5nm manufacturing process. Read More...

PicoZed SDR enables application-level design

Avnet’s PicoZed SDR system-on-module combines Analog Devices' AD9361 RF agile transceiver with a Xilinx Zynq-7035 all-programmable SoC. Read More...

Evaluation kit jumpstarts FPGA embedded design

Arty is a customizable evaluation kit from Avnet that allows developers to prototype low-power designs based on the Xilinx Artix-7 35T FPGA. Read More...

SmartFusion2 development kit comes with JTAG emulator

Based on a SoC FPGA with embedded security, Avnet’s SmartFusion2 KickStart kit enables the prototyping of low-power, high-security IoT designs. Read More...

FPGA IP cores enable flexible SoC design

Optimized for TSMC’s 28-nm process, Menta’s predefined off-the-shelf IP cores for complex SoC devices simplify post-production customization. Read More...

Knowm's memristors alive & shipping

True bidirectional memristors are now available for experimentation as well as integration onto CMOS chips, enabling machine learning and other breakthrough apps. Read More...

ClioSoft updates EDA management platform

Version 7.0 of ClioSoft’s SOS design data and enterprise IP management platform is up to 30 times faster than previous versions. Read More...

Toshiba launches 256-Gbit 48-layer 3-D NAND flash

Ready for sampling in September, Toshiba’s 48-layer BiCS flash memory stores 256 Gbits using a 3-D vertically stacked cell structure. Read More...

Boundary-scan viewer offers trace imaging

Version 8.2 of the ScanExpress boundary-scan tool suite from Corelis adds trace imaging using ODB++ netlist data. Read More...

Globalfoundries launches FD-SOI processes

Globalfoundries Inc. has announced that it is offering a 22nm FD-SOI manufacturing platform that can operate down to 0.4V. Read More...

Artix-7 FPGA drives PC/104 I/O board

The EMC2-7A I/O board from Sundance integrates a PCI Express x4 Gen2 interface and reprogrammable logic on a PC/104 form factor called OneBank. Read More...

Pushing emulation beyond functional tests

With the launch of its Veloce Power Application software, Mentor Graphics advocates for the emulation of large SoCs beyond the typical sets of functional tests. Read More...

Fine-grained power architecture eases SoC design

Mainstream SoC design teams can use the ICE-Grain (Instant Control of Energy) power architecture from Sonics to automate power-management schemes that employ finely grained SoC partitions for use in a myriad of energy-sensitive consumer, IoT, mobile, wearable, automotive, and set-top box applications. Read More...

RF SOI process design kit leverages PSP-SOI model

Targeting both advanced wireless and wired applications, pure-play 200-mm foundry Shanghai Huahong Grace Semiconductor Manufacturing (HHGrace) and Gildenblat Consulting, a semiconductor modeling service and consulting company, jointly announced a 0.2-µm RF SOI (silicon-on-insulator) PDK (process design kit) containing Gildenblat’s PSP-SOI model. Read More...

Quartus gets under-the-hood reboot

Altera has released a new engine for its Quartus II software to scale up with the increasing density of large FPGAs. Read More...

Online portal speeds ASIC quotation process

To facilitate and improve the turnaround time for ASIC quotations, Open-Silicon has created a web portal for customers to submit their system requirements. Read More...

Fast extraction tool maintains high accuracy

Calibre xACT, a parasitic extraction platform from Mentor Graphics, provides attofarad accuracy and the ability to handle multimillion-instance designs to address a wide range of analog, digital, custom, and RF extraction requirements, including 14-nm FinFET. Read More...

Two-channel SMU sources and sinks

The GS820 source-measure unit from Yokogawa is available in 18 V and 50 V models. Read More...

Quantum computer kit announced – Save over $10,000,000!

The most exciting announcement this editor has ever covered: Quantum computing for the masses. Read More...

Xpedition Package Integrator spans IC chip to package to PCB

Mentor's new Package Integrator allows co-design of chips, single- & multi-chip packaging, and PCB layout. Read More...

Innovus Implementation System claims up to 10× turnaround time reduction

Cadence's new Innovus Implementation System shows impressive speedups and PPA results. Read More...

GaN transistor boosts efficiency, power density

Transphorm is offering engineering samples of the TPH3205WS, a 600-V GaN transistor in a small 3-pin TO-247 package that delivers high-efficiency operation in 80 Plus Titanium-class power-supply and inverter applications up to 3 kW. Read More...

One-stop-shop from IC design to silicon tape out

CEA-Leti has launched the Silicon Impulse IC design competence centre, offering IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles. Read More...

Extensible processor IP offers up to 75% memory power and area savings

Xtensa LX6 and Xtensa 11 processors enable users to create innovative custom processor instruction sets with up to 25% less processor logic power consumption and up to 75% better local memory area and power efficiency. Read More...

Catapult 8 a major HLS upgrade

Calypto is calling Catapult 8 "third generation" high-level synthesis technology, and it supports both C++ and SystemC. Read More...

PXI module exercises and characterizes DIO channels

The GX5295 from Marvin Test Solutions lets you add 32 DIO channels with source/sink capabilities to an PXI instrument chassis. Read More...

FPGA boards under $100: Altera/Terasic DE0-Nano

A close look at the Cyclone IV-based $79 DE0-Nano FPGA devboard from Terasic. Read More...

EDN Hot 100 products of 2014: EDA Tools, IP & Memory/Storage

This section of EDN's Hot 100 Products of 2014 includes design automation tools and memory/storage products. Read More...

FPGAs said to be industry’s most secure

Microsemi's ultra secure SmartFusion2 SoC FPGAs and IGLOO2 FPGAs are claimed to have more advanced security features at the device, design and system levels than any other leading FPGA. Read More...

Tabula FPGA provides 100% observability

Tabula's DesignInsight technology has the potential to provide a step-function improvement in development time and cost. Read More...

100 GHz real-time oscilloscope arrives

Teledyne LeCroy ups the oscilloscope bandwidth ante with the announcement of the LabMaster 10-100Zi. Read More...

Verification IP for 3D memory structures

Cadence Design Systems has announced verification IP supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube, High Bandwidth Memory, and DDR4 3D Stacking. Read More...

Memory IP targets low power requirements

In order to reach the stringent low power requirements of LCD drivers and touch screen controllers, Dolphin Integration has introduced a foundry-sponsored Single port RAM for the UMC 110 nm embedded Flash process. Read More...

MAX10 broadens the FPGA field

Altera's MAX series has graduated from CPLD to FPGA, and sports some unique features. Read More...

Audio analyzer claims world's lowest noise

Audio Precision's APx555 bridges the gap between bench and production testing while providing -117 dB of THD+N. Read More...

Mil temp-qualified FPGAs in 20-nm

Mil temp-qualified Arria 10 FPGAs and SoCs will allow military customers to make early specification decisions in designing avionics, radar and other high reliability applications, Altera says. Read More...

Cadence unveils Protium FPGA-based SoC prototyping platform

Protium puts two to eight Virtex-7 FPGAs under the hood to help you prototype & test complex SoCs. Read More...

>> SEE ALL

Teardown: Apple iPhone 6 Plus battery

A look at Apple's iPhone 6 battery helps nail down the one variable that determines manufacturing cost. Read More...

1969 Compucorp calculator teardown

A 1969 scientific calculator teardown. This one's got them newfangled ICs. Read More...

Teardown: 1966 Programmable scientific calculator

Look inside a mid-1960s programmable scientific calculator! Read More...

Integration amassed: analyzing a NAS

This hands-on project showcases the second generation of Western Digital's My Book World Edition NAS (network-attached storage) device, so named because it is potentially accessible by a user from anywhere in the world. Read More...

One sensor does the work of many

The single-array camera captures images that conventionally require an array of sensors. Read More...

Inside the Schick Hydro microcontroller-powered wet razor

Though the shaving experience may be overrated, a look inside the Schick Hydro reveals another unexpected application for microcontrollers—in this case a less-than-$1 PIC10F222 from Microchip. Read More...

Artificial cochlea: an example of structural processing

Prying Eyes: A MEMS-based artificial cochlea mimics the real thing in form and function. Read More...

TV peripheral encompasses superset processor

Prying Eyes looks inside the Delkin eFilm Picturevision, which enables the playback of audio, still-image, and video files on a variety of memory-card formats. Read More...

Teardown: The nuances of variable-frequency drives

Get an inside view of induction-motor control by varying frequency using PWM. Read More...

>> SEE ALL

ARM intrusive debugging for post-silicon SoC validation

Read about debugging options and examples for complex SoC designs. Read More...

Source synchronous interface timing closure

Learn about different types of source-synchronous interface and their timing challenges. Read More...

Choosing a mobile-storage interface: eMMC or UFS

Consider the pros and cons of these evolving standards for your next SoC or system design. Read More...

The future of IC design

By 2076, 3D room-temperature, superconducting, quantum, neuromorphic, and photonic mixed-signal devices will be the common denominator for all integrated circuit designs. Read More...

FPGA constraints for the modern world: Product how-to

Writing design constraints can be onerous; tools can help. Read More...

10 Ways to program your FPGA

Go way beyond the Verilog/VHDL basics. Read More...

Proper oscilloscope setup yields correct ESD measurements

To get the right measurements of ESD pulses, you need to set trigger levels properly and use as much of the ADC as possible. Read More...

Free yourself from IBIS-AMI models with PyBERT

PyBERT, an open-source modeling tool, can help you design high speed SERDES devices and systems. Read More...

Timing-aware pipelining optimization for area reduction

This algorithm results in a useful chip area reduction. Read More...

Validate USB host designs with a bare metal driver

When implementing a USB hub you'll need to validate the design. Creating a bare metal driver for handling a Flash drive can help. Read More...

Large-panel QFN leadframes reduce costs but bring assembly challenges

Conversion to the largest QFN leadframe panels will reduce costs, as long as the challenges are overcome. Read More...

Software-defined FPGA computing with QuickPlay: Product how-to

A new FPGA design methodology allows software engineers to build high-performance computing engines based on FPGAs, using familiar tools and techniques. Read More...

Resolve picoseconds using FPGA techniques

Performing timing measurements in the picosecond range (for oscilloscope triggering say) requires sophisticated and fast circuitry, but an off-the-shelf FPGA combined with some lateral thinking provides better results than at first seem possible! Read More...

>> SEE ALL

Verification “escapes” leave bugs in silicon

Here’s practical advice to stop bugs from getting through, or “escaping”, verification. Read More...

Electrical engineering in the 1960s: The transistor changed everything

Everything we do today in electronics is based on the transistor, but it wasn't always that way. Here's how one engineer described what happened when transistors came along. Read More...

Resets in FPGA & ASIC control and data paths

Don’t take resets for granted in your design. Read More...

28nm was last node of Moore's Law

The industry is at a crossroads: some designs pursue scaling to 7nm while the majority stay on 28nm or older nodes. Read More...

19 Views of Hot Chips

The annual Hot Chips event reflected a semiconductor industry moving rapidly in multiple directions with a lot of energy pouring into machine learning, smarter cars and novel sensors. Read More...

Back-annotating DFM enhancements to place & route tools

By enabling back-annotation of DFM shapes and information to P&R, file translation can also help to reduce iterations and close timing while ensuring the optimized layout remains DRC-compliant. Read More...

What DFT history teaches us

An EDN article from 1988 shows the state of design for test at that time, now see how it has evolved. Read More...

Electromigration protection requires accurate interconnect modeling

Learn about electromigration and how to deal with it. Read More...

Zero-mask-adder NVM vs. Embedded flash

A zero-mask-adder NVM solution for SoCs can be more economical than embedded flash. Read More...

IC Debugging: Simulation vs. Lab validation

IC design verification has been the biggest challenge for decades now. Read how simulation fits in. Read More...

SoC Spec defines core interfaces

HSA version 1.1 defines IP block interfaces. Read More...

DAC 2016 in pictures

The buzz from the 53rd DAC in Austin. Read More...

Experiences with hardware emulation

The 2016 Mentor Graphics' User Group boasted five technical sessions focused on emulation. Read More...

Vacuum tube technology resurrected

On this 60th anniversary of EDN, we look back to 1956 when the vacuum tube was at its maturity and transistors were about to begin their domination. Read More...

Use VUnits for assertions & functional coverage

VUnits help in the reduction of hundreds of lines of assertions and functional coverage to smaller pieces of code. Read More...

Understanding WGL scan data structures and some common issues

The way in which scan is handled within WGL files is often a source of confusion for engineers. Read More...

Efficient parasitic extraction techniques for full-chip verification

Hierarchical and selective net extraction provides numerous benefits in chip-level verification. Read More...

PAM & Ethernet: A perfect match

Look at the PAM (pulse-amplitude modulation) variants used throughout Ethernet’s history, and some verification IP to help you become part of that history, not a footnote in it. Read More...

EDN turns 60, help us celebrate

EDN began life as Electrical Design News on May 8, 1956. Here's what to expect over the coming months as we celebrate the publication. Read More...

HDL Coding styles

Look at a range of HDL coding styles. Read More...

Moortec discusses on-chip PVT monitoring

As Moortec’s CTO, Oliver King has been leading the development of compelling on-chip monitoring solutions to address problems associated with ever-shrinking SoC geometries. Read More...

Efficient data inspection techniques for colossal memory designs

Reduce debug, simulation, and verification times in large-memory systems. Read More...

Speed FPGA debug

A versatile, iterative, and incremental debug methodology allows FPGA designers to deliver debugged designs quickly and easily. Read More...

Designer's Notebook: Discrete Logic

In the age of FPGA and CPLD, there's still a place for discrete logic. Read More...

Take scan test out of the critical path

Design for test and pattern recognition are shifting left, moving up in the IC design cycle. Read More...

What's behind Keysight's 100 GHz announcement?

Keysight Technologies announced Indium Phosphide technology that will let the company jump to the top of the oscilloscope bandwidth race. As a benefit, the company has a 10-bit ADC. Read More...

UVCs save time in SoC verification

Learn how UVCs can speed and improve SoC verification. Read More...

Inside a quantum computing lab

Take a tour of the Institute for Quantum Computing at the University of Waterloo. Read More...

New generation of physical RTL synthesis improves QoR

Optimizing at the RTL level offers more room for QoR improvement than gate-level optimization, in addition to enabling higher capacity and faster runtimes. Read More...

High bandwidth memory (HBM) PHY IP verification

Read about the verification aspects and challenges of HBM IP. Read More...

Power Integrity: It's not just decoupling caps

The field of power integrity (PI) is exploding. Discover how complicated today's PDNs have become, and consider making yourself into a domain expert so that your next design isn't sunk by a rogue wave! Read More...

Hierarchical floorplanning comes of age

GUI-driven hierarchical floorplanning capabilities make big improvements in quality, time-to-tapeout, and design costs. Read More...

Enable IoT ASIC Design Using Platforms

It may seem premature to be talking about ASICs for IoT designs, but the platform approach can make IoT ASICS practical. Read More...

2016 Predictions for mixed-signal IC design

Complex mixed-signal SoC verification requires a system-level view—encompassing chip, package, and board—to ensure high-quality chips for application areas like automotive and IoT. Read More...

Accurate memory models for all

Accurate memory models are fundamental to SoC verification. Read about what to look for in models, and what the author likes about his company’s offering. Read More...

>> SEE ALL

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