datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com   UBM Tech
UBM Tech

IC Design

Suzanne Deffree
Editor
Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, related semiconductor manufacturing, and the design methodologies other IC designers are using to become successful.

An intelligent scan-stitched architecture for better ATPG test efficiency

Distributing the flops of individual IP in different chains helps remove clustering of scan flops, resulting in improved ATPG efficiency. Read More...

Semiconductor Reliability and Quality Assurance--Failure Mode, Mechanism and Analysis (FMMEA)

This article introduces how to implement FMMEA in detail, including system definition, identification of potential failure modes, analysis of failure cause, failure mechanism, and failure effect analysis. Read More...

See the crosstalk in 100GbE

Thrill to a real-time view of time-varying 25Gb/s crosstalk. Read More...

Part Average Testing finds and rejects outlier ICs

There's a small tradeoff in the resulting lower yield, but Part Average Testing can weed out long-term failures. Read More...

Companion FPGA packs 85K LUTs in 10x10mm package

The ECP5 FPGA Family was specifically designed to focus on key fast growing and high-volume markets such as small-cells, microservers, broadband access, or industrial video. Read More...

Remembrance of chips past

A look at some ICs from a kinder, simpler time. Read More...

Apex Microtechnology shows why hybrid ICs are still valuable to the electronics industry

I recently visited Apex Microtechnology, a privately held manufacturer of precision power analog monolithic, hybrid and open-frame components in Tucson, AZ. Read More...

Leakage power optimization for 28nm and beyond

Achieve major leakage current reduction by following the methodology described in this article. Read More...

Piling functionality and its impact on packaging manufacturing and reliability

Packaging engineers must understand the dynamics of development, qualification, and HVM of FCBGA packages to keep pace with the ever-changing demands of industrial and automotive applications. Depending on the approach, the drive for higher performance can lead packaging engineers to either great rewards or great pains. Read More...

SDC: WTH?

Is SDC crazy, or am I? How do you specify your FPGA timing? Read More...

Open FPGAs add flexibility to test

With access to an instrument's FPGA, you can add measurement science to your test applications. Read More...

IDDQ failure diagnosis is here

Once deemed too good to be true, then deemed obsolete, IDDQ testing can now provide information as to why a semiconductor device failed. Read More...

SoC interconnect architecture considerations

Given that many SoCs nowadays are comprised of a plethora of such blocks, the interconnect architecture can be a key differentiator among the SoCs. Read More...

Upverter Web EDA gets major revamp

The Web-based capture/simulation/PCB service gets a big facelift. Read More...

Embedding components within PCB substrates

Embedding components within a PCB substrate offers a range of benefits in terms of space and performance. But this alternative approach to product design demands support from the entire supply chain, including EDA vendors. Read More...

Redundancy for safety-compliant automotive & other devices

Learn the many kinds of HW & SW redundancy that can be applied to safety-critical systems and SoCs. Read More...

Challenges associated with Digital-Analog combined IP’s

This paper discusses in detail challenges with Digital-Analog combined IP and details certain steps that should be followed for faster and robust verification signoff of such Mixed Signal IP’s. Read More...

Restraining the impact of wire resistance at 28nm and 16nm semiconductor process nodes

With process geometries shrinking beyond 28nm, process characteristics are becoming more complex with increasing wire resistance. Read More...

Overcoming FPGA board design challenges

The FPGA world can be an overwhelming place for newbies and seasoned pros alike. Need an FPGA on your board? Here are some tips and starting points. Read More...

Gate level simulations: verification flow and challenges

Despite being a time consuming activity and having many challenges in setup and debug, gate level simulation can uncover certain hidden issues that are missed out or difficult to find by RTL simulations. Read More...

>> SEE ALL

Single-cycle logarithms & antilogs

Here are some very fast log (and antilog) blocks well-suited to FPGA implementation. Read More...

Postprocessing converts Spice to RF analyzer

Designers of RF and high-frequency products need a simulator that can predict noise figure at a given frequency, minimum noise figure, optimum reflection coefficient for noise, and noise resistance. Read More...

Build a UWB pulse generator on an FPGA

Make pulses that reach twice an FPGA's clock frequency. Read More...

SDRAM interface slashes pin count

Many designs need deep buffering but don't require ultrahigh-memory bandwidth. Examples include image and audio processing, as well as some deep-FIFO applications. These designs often use a singlex8 SDRAM device that connects to an FPGA or ASIC. This approach solves the buffering problem but also burns a lot of valuable pins, which can be as many as 27 for a single SDRAM device. Read More...

Design provides single-port-to-dual-port SDRAM converter

Read and write operations won't interfere with each other. Read More...

Compute a histogram in an FPGA with one clock

Use a histogram to analyze large amounts of data. Read More...

PRBS generator runs at 1.5 Gbps

FPGA and serializer generate fast sequences to test communications links. Read More...

Decode a quadrature encoder in software

Use a microcontroller to decode signals without the need for a dedicated IC. Read More...

VHDL program enables PCI-bus-arbiter core

A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters. Read More...

Capacitive touch switch uses CPLD

Using an Altera MAX IIZ CPLD, you can implement a touch-switch decoder with no external components. Read More...

Swapping bits improves performance of FPGA-PWM counter

A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC. Read More...

Active multiplexing saves inputs

Add an inverter to reduce current and diodes to route inputs to a microcontroller's inputs as needed. Read More...

Perform hexadecimal-to-BCD conversion in firmware

Converting in firmware eliminates a conversion chip. Read More...

Implement a simple digital-serial NRZ data-recovery algorithm in an FPGA

A shift register and some logic lets you recover embedded clocks from data streams. Read More...

ADC for programmable logic uses one capacitor

Use a capacitor's charging and discharging time to sense a user input. Read More...

Stepper-motor motion controller and driver fit into a CPLD/FPGA

A CPLD or FPGA can be a home for a stepper-motor motion controller and driver. Read More...

Implement a stepper-motor driver in a CPLD

Replace a hard-to-find stepper-motor-driver IC with a programmable-logic device. Read More...

Add a Schmitt-trigger function to CPLDs, FPGAs, and applications

For slow-slewing signals, hysteresis solves trigger problem. Read More...

Three-phase digital-signal generator sweeps frequency

Use a clock divider to sweep frequency by 20 kHz. Read More...

Microcontroller drives piezoelectric buzzer at high voltage

Drive the buzzer directly from the μC’s I/O pins. Read More...

>> SEE ALL

Companion FPGA packs 85K LUTs in 10x10mm package

The ECP5 FPGA Family was specifically designed to focus on key fast growing and high-volume markets such as small-cells, microservers, broadband access, or industrial video. Read More...

Software library enables FPGA-based drive control

The XSG AC Motor Control Library from software tool vendor dSpace speeds the development of Xilinx FPGA-based motor control designs. Read More...

Debugger teams with ARM’s System Trace Macrocell

Enhancements to Asset InterTech’s Arium hardware-assisted SourcePoint debugger optimize the processing of ARM’s System Trace Macrocell (STM), which provides developers of multicore, multithreaded SoCs a system-level perspective of trace data. Read More...

Software eases interconnect analysis of ARM-based SoCs

Interconnect Workbench from Cadence provides interconnect performance analysis and verification of SoC (system-on-chip) devices incorporating ARM CoreLink CCI-400, NIC-400, NIC-301, and ADB-400 system intellectual property (IP). Read More...

Hypervisor delivers security for multicore processors, enables multi-OS consolidation

Mentor Graphics has introduced an embedded hypervisor product for in-vehicle infotainment systems, telematics, advanced driver assistance systems, and instrumentation. Read More...

FastSPICE simulator offers up to 10X faster throughput

Cadence has introduced Spectre XPS (eXtensive Partitioning Simulator), featuring a breakthrough partitioning technology, that enables higher capacity and faster simulation while requiring two to three times less system memory. Read More...

Synopsys aims at TVs with ARC-based Dolby MS11 decoder

Synopsys' DesignWare IP for ARC Audio Processors has been augmented with support for Dolby Laboratories' Multistream Decoding, expanding the portfolio of ARC audio codecs. Read More...

System builder design tool targets ARM-based SmartFusion2 SoC FPGAs

Microsemi's System Builder is a new design tool within the Libero System-on-Chip (SoC) Design Environment version 11.0 and is specifically targeted at accelerating customer definition and implementation of ARM-based systems using SmartFusion2 SoC FPGAs. Read More...

FPGA/SoC families debut with performance boost, power reduction

Altera has announced its Generation 10 family comprising its Arria 10 and Stratix 10 series of FPGAs and SoCs. Read More...

Requirements lifecycle management tool targets safety-critical FPGA and ASIC design

Aldec's Spec-TRACER is a requirements lifecycle management solution for use in safety-critical industries in which rigorous certification standards exist; such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear. Read More...

Virtex 7-based FPGA module targets multi FPGA prototyping

Pro Design has added the proFPGA V7 mini FPGA module to its family of FPGA based prototyping solutions. Read More...

EDN Hot 100 products of 2012: EDA/IP and memory/storage

This section of EDN's Hot 100 Products of 2012 includes design automation software and memory/storage products. Read More...

Fully integrated ETSI category 1 transceiver cuts 50% from cost and size

The CC1125 sub-1 GHz RF transceiver is a single-chip solution for wireless social alarms and ultra narrowband applications Read More...

Noise-cancelling ICs improve wireless headset audio quality

The AS3421, AS3422 single-chip ANC solutions feature an integrated speaker driver optimized for Bluetooth-enabled headset SoCs. Read More...

Voltage detector combines 0.58V reference and resettable latched comparator

The TS12001 voltage detector by Touchstone Semiconductor operates from a single 0.65V to 2.5V power supply and consumes less than 1μA total supply current. Read More...

Unified software environment makes engineers efficient

DIAdem 2012 is a single, unified software environment that makes engineers more efficient when locating, inspecting, visualizing, analyzing and reporting on data. Read More...

Detection and configuration switch IC enriches audio headset experience

The TS3A225E audio headset detection and configuration switch IC enables universal headset support for audio apps in a single chip. Read More...

Op amp, comparator and reference IC combo cuts power 10x

The TS12011 and TS12012 are 1.2μW op amp, comparator and voltage reference in one IC. Read More...

APM8669x processors enable domain protection for advanced system partitioning

The Black Mamba APM8669x is the highest performing member of the PacketPro2 family of multicore processors. Read More...

First silicon of Virtex-7 heterogeneous 3D FPGA ships

The Virtex-7 H580T, the first heterogeneous 3D FPGA is now shipping to key customers. Read More...

NPI software links PCB design and manufacturing operations

Mentor Graphics’ Valor NPI (new product introduction) software is now fully integrated with the company’s Xpedition PCB design platform to deliver a seamless, automated flow for the design, fabrication, and assembly of PCBs. Read More...

Automated embedded test targets differential clock signals

Goepel electronic has released an extension of its ChipVORX embedded test instruments for universal frequency measurement based on special FPGA soft macros. Read More...

IPEmotion software gets CAN traffic analyzer, improved visualization

Automotive measurement technology provider Ipetronik has introduced version 2014 R1 of its popular IPEmotion data acquisition software. Read More...

>> SEE ALL

Teardown: The power inverter - from sunlight to power grid

This teardown of a solar inverter card traces the path of harvested DC power from the photovoltaic panel, through boost conversion, power inverter and massive filtering of the created AC power signal required by the power grid. Surrounded by monitoring and microcontroller magic along with safety standard adherence, we uncover the mysteries of solar energy harvesting electronics. Read More...

Integration amassed: analyzing a NAS

This hands-on project showcases the second generation of Western Digital's My Book World Edition NAS (network-attached storage) device, so named because it is potentially accessible by a user from anywhere in the world. Read More...

One sensor does the work of many

The single-array camera captures images that conventionally require an array of sensors. Read More...

Inside the Schick Hydro microcontroller-powered wet razor

Though the shaving experience may be overrated, a look inside the Schick Hydro reveals another unexpected application for microcontrollers—in this case a less-than-$1 PIC10F222 from Microchip. Read More...

Artificial cochlea: an example of structural processing

Prying Eyes: A MEMS-based artificial cochlea mimics the real thing in form and function. Read More...

TV peripheral encompasses superset processor

Prying Eyes looks inside the Delkin eFilm Picturevision, which enables the playback of audio, still-image, and video files on a variety of memory-card formats. Read More...

Teardown: The nuances of variable-frequency drives

Get an inside view of induction-motor control by varying frequency using PWM. Read More...

>> SEE ALL

An intelligent scan-stitched architecture for better ATPG test efficiency

Distributing the flops of individual IP in different chains helps remove clustering of scan flops, resulting in improved ATPG efficiency. Read More...

Semiconductor Reliability and Quality Assurance--Failure Mode, Mechanism and Analysis (FMMEA)

This article introduces how to implement FMMEA in detail, including system definition, identification of potential failure modes, analysis of failure cause, failure mechanism, and failure effect analysis. Read More...

Piling functionality and its impact on packaging manufacturing and reliability

Packaging engineers must understand the dynamics of development, qualification, and HVM of FCBGA packages to keep pace with the ever-changing demands of industrial and automotive applications. Depending on the approach, the drive for higher performance can lead packaging engineers to either great rewards or great pains. Read More...

Open FPGAs add flexibility to test

With access to an instrument's FPGA, you can add measurement science to your test applications. Read More...

Guarding chips against "electric floods"

Composed of minute charged particles, electrical current naturally flows from the higher voltage to lower; like a river flowing from the mountains to the sea. Read More...

SoC interconnect architecture considerations

Given that many SoCs nowadays are comprised of a plethora of such blocks, the interconnect architecture can be a key differentiator among the SoCs. Read More...

Embedding components within PCB substrates

Embedding components within a PCB substrate offers a range of benefits in terms of space and performance. But this alternative approach to product design demands support from the entire supply chain, including EDA vendors. Read More...

Redundancy for safety-compliant automotive & other devices

Learn the many kinds of HW & SW redundancy that can be applied to safety-critical systems and SoCs. Read More...

Leading-edge adoption trend, any feeling of déjà vu?

The usual semiconductor industry trend that segments technology node adoption into leading-edge adopters, followers, and the so-called “trailing edge” has been disrupted for the 20nm technology node as the 2× reduction in cost per transistor seen from technology node to technology ends after 28nm. Read More...

Challenges associated with Digital-Analog combined IP’s

This paper discusses in detail challenges with Digital-Analog combined IP and details certain steps that should be followed for faster and robust verification signoff of such Mixed Signal IP’s. Read More...

Overcoming FPGA board design challenges

The FPGA world can be an overwhelming place for newbies and seasoned pros alike. Need an FPGA on your board? Here are some tips and starting points. Read More...

Gate level simulations: verification flow and challenges

Despite being a time consuming activity and having many challenges in setup and debug, gate level simulation can uncover certain hidden issues that are missed out or difficult to find by RTL simulations. Read More...

Smaller scale chip design relies on creative thinking and collaborative workflow

This case study illustrates Nextivity’s chip design process, with the intent of providing other small organizations with creative and collaborative workflow ideas that can be applied in their own chip design environments. Read More...

General purpose input-output PAD: Cases of drive-contention

In this article the basic circuitry of any I/O pad will be discussed with an insight into why we need the specific circuits at all. Read More...

Efficient analysis of CDC violations in a million gate SoC, part 2

One interesting topic of discussion is whether to use synchronous or asynchronous reset in design. Read More...

Efficient analysis of CDC violations in a million gate SoC, part 1

With the increasing complexity of SoC, multiple and independent clocks and resets are essential in the design. Here, Clock Domain Crossings (CDC) are a potential source of design errors. Read More...

Conversion algorithm of SAR ADC and Cyclic ADC with an analysis of importance of reference voltages

In this paper our attention will be on quantization. So what we will discuss is when data has to be quantized, how we can find the correct digital equivalent for the data from the complete set of 2N (N being the resolution of the ADC). Read More...

Decreasing parasitic capacitance in IC layouts

As the semiconductor industry grows so does the density of devices on chip. With the increasing density and decreasing spacing rules, the most significant effect that takes birth is parasitic. Read More...

A novel partitioning strategy for analog routes for hierarchical designs

In this paper we propose a partitioning approach that helps take care of the complexities that come into picture while integrating these blocks in SOC. Read More...

Synchronizing handshaking between data converters and high speed digital data acquisition systems Part three

Part one of this three part article described data converter characterization, the conversion process, data acquisition systems and the HSDIO card and logic analyzer. Part two went into real time data capture and jitter. And now on to the final Part three. Read More...

>> SEE ALL

FEATURED RESOURCES