ESC

IC Design

Michael Dunn
Editor, Design Ideas, IC/FPGA, PCB, and Medical Design Centres
Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, related semiconductor manufacturing, and the design methodologies other IC designers are using to become successful.

Which software automates your tests?

A poll on EE Times asks which of several software packages engineers use to automate tests. Tell us which you use. Read More...

Pushing emulation beyond functional tests

With the launch of its Veloce Power Application software, Mentor Graphics advocates for the emulation of large SoCs beyond the typical sets of functional tests. Read More...

A Case Study - RF ASIC Validation of a satellite transceiver

ASIC validation in the RF world comes with its own set of hurdles and challenges, with high quality lab equipment, experience and know-how essential. A recently completed RF sub-system validation at S3 Group is presented in the form of a case study of the execution. The validation PCB design focussed on impedance matching and shielding RF signals from noise sources. We built up an efficient, automated test harness based on LabVIEW, MATLAB and python. This unified test framework facilitated instrument set-up, test-case running, data collection, traceability, plotting of measurements, waveform generation and analysis. Read More...

RF SOI process design kit leverages PSP-SOI model

Targeting both advanced wireless and wired applications, pure-play 200-mm foundry Shanghai Huahong Grace Semiconductor Manufacturing (HHGrace) and Gildenblat Consulting, a semiconductor modeling service and consulting company, jointly announced a 0.2-µm RF SOI (silicon-on-insulator) PDK (process design kit) containing Gildenblat’s PSP-SOI model. Read More...

Matrix-based clock verification uncovers SoC bugs

Using the matrix based clock verification approach, we were able to cover corner-case scenarios and find about twenty critical design bugs across three SoCs. Read More...

Reverse bias techniques for high-end automotive microcontrollers & low leakage

A reverse-bias technique to reduce leakage, especially at high temperature (e.g., automotive). Read More...

The 7 levels of IP verification

IP quality should lead your list of SoC requirements. Here’s how to assess it. Read More...

Simulate digital filters with PSpice

PSpice isn’t just for analog! This Design Idea shows it can handle digital filter simulation too. Read More...

Three ways the 3-terminal resistor model improves power converter circuits

Change the way power MOSFETs are modeled to increase the odds of first-pass power IC design success. Read More...

Quartus gets under-the-hood reboot

Altera has released a new engine for its Quartus II software to scale up with the increasing density of large FPGAs. Read More...

VCS commands ease coverage efforts & speed simulation

By using certain functions and commands in SystemVerilog and the Synopsys VCS tool, one can reduce coverage closure effort as well as the resultant simulation time. Read More...

Online portal speeds ASIC quotation process

To facilitate and improve the turnaround time for ASIC quotations, Open-Silicon has created a web portal for customers to submit their system requirements. Read More...

A SystemC-based UVM verification infrastructure

TVS has made a SystemC library to enable UVM verification to be performed using SystemC rather than System Verilog freely available. Read More...

Simplified kurtosis computation detects signal interference

The statistical kurtosis operation, reinterpreted and implemented on an FPGA for this Design Idea, can detect various forms of interference in RF and other signals. Read More...

Fast extraction tool maintains high accuracy

Calibre xACT, a parasitic extraction platform from Mentor Graphics, provides attofarad accuracy and the ability to handle multimillion-instance designs to address a wide range of analog, digital, custom, and RF extraction requirements, including 14-nm FinFET. Read More...

Security architecture for automotive microcontroller flash memory

Read about various ways flash memory can be secured against malicious or accidental modification. Read More...

Linear Technology knows how to make a Power uModule

There is an art to designing a power supply that is fully enclosed in a compact molded plastic package. Read More...

Verilog-AMS vs. SPICE view: An SoC verification comparison

It is important to weigh the pros and cons of a Verilog/Verilog-AMS view versus a SPICE view for all the analog blocks and IPs within a SoC. Read More...

Kintex-7, SEU mitigation using an isolated-design flow, part 1

Replicating and isolating redundant logic blocks within an FPGA fabric offers the potential of fault-tolerant implementation, confining SEUs to a single module preventing their propagation. Read More...

>> SEE ALL

Simplified kurtosis computation detects signal interference

The statistical kurtosis operation, reinterpreted and implemented on an FPGA for this Design Idea, can detect various forms of interference in RF and other signals. Read More...

NRZ to AMI converter uses single supply

Convert serial data to AMI format with this simple Design Idea. Read More...

Circuit gates pulse train without truncating

This Design Idea accomplishes asynchronous gating without the worry of shortened pulses. Read More...

Anti-symmetric FIR filter slashes resource use

An anti-symmetric FIR design with the same implementation advantage as a symmetric. Read More...

Monolithic PWM generator runs fast, minimizes silicon

This analog-based PWM generator Design Idea does away with amplifiers and comparators to minimize space and power. Read More...

Single-cycle logarithms & antilogs

Here are some very fast log (and antilog) blocks well-suited to FPGA implementation. Read More...

Build a UWB pulse generator on an FPGA

Make pulses that reach twice an FPGA's clock frequency. Read More...

SDRAM interface slashes pin count

Many designs need deep buffering but don't require ultrahigh-memory bandwidth. Examples include image and audio processing, as well as some deep-FIFO applications. These designs often use a singlex8 SDRAM device that connects to an FPGA or ASIC. This approach solves the buffering problem but also burns a lot of valuable pins, which can be as many as 27 for a single SDRAM device. Read More...

Differential amp has 6dB lower noise, twice the bandwidth

Differential/instrumentation amp topologies possess varying trade-offs. Here’s one that improves noise & BW at the expense of input resistance. Read More...

Design provides single-port-to-dual-port SDRAM converter

Read and write operations won't interfere with each other. Read More...

Compute a histogram in an FPGA with one clock

Use a histogram to analyze large amounts of data. Read More...

PRBS generator runs at 1.5 Gbps

FPGA and serializer generate fast sequences to test communications links. Read More...

VHDL program enables PCI-bus-arbiter core

A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters. Read More...

Postprocessing converts Spice to RF analyzer

Designers of RF and high-frequency products need a simulator that can predict noise figure at a given frequency, minimum noise figure, optimum reflection coefficient for noise, and noise resistance. Read More...

Decode a quadrature encoder in software

Use a microcontroller to decode signals without the need for a dedicated IC. Read More...

Capacitive touch switch uses CPLD

Using an Altera MAX IIZ CPLD, you can implement a touch-switch decoder with no external components. Read More...

Swapping bits improves performance of FPGA-PWM counter

A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC. Read More...

Active multiplexing saves inputs

Add an inverter to reduce current and diodes to route inputs to a microcontroller's inputs as needed. Read More...

Perform hexadecimal-to-BCD conversion in firmware

Converting in firmware eliminates a conversion chip. Read More...

Implement a simple digital-serial NRZ data-recovery algorithm in an FPGA

A shift register and some logic lets you recover embedded clocks from data streams. Read More...

ADC for programmable logic uses one capacitor

Use a capacitor's charging and discharging time to sense a user input. Read More...

Stepper-motor motion controller and driver fit into a CPLD/FPGA

A CPLD or FPGA can be a home for a stepper-motor motion controller and driver. Read More...

Implement a stepper-motor driver in a CPLD

Replace a hard-to-find stepper-motor-driver IC with a programmable-logic device. Read More...

Add a Schmitt-trigger function to CPLDs, FPGAs, and applications

For slow-slewing signals, hysteresis solves trigger problem. Read More...

Three-phase digital-signal generator sweeps frequency

Use a clock divider to sweep frequency by 20 kHz. Read More...

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Pushing emulation beyond functional tests

With the launch of its Veloce Power Application software, Mentor Graphics advocates for the emulation of large SoCs beyond the typical sets of functional tests. Read More...

Fine-grained power architecture eases SoC design

Mainstream SoC design teams can use the ICE-Grain (Instant Control of Energy) power architecture from Sonics to automate power-management schemes that employ finely grained SoC partitions for use in a myriad of energy-sensitive consumer, IoT, mobile, wearable, automotive, and set-top box applications. Read More...

RF SOI process design kit leverages PSP-SOI model

Targeting both advanced wireless and wired applications, pure-play 200-mm foundry Shanghai Huahong Grace Semiconductor Manufacturing (HHGrace) and Gildenblat Consulting, a semiconductor modeling service and consulting company, jointly announced a 0.2-µm RF SOI (silicon-on-insulator) PDK (process design kit) containing Gildenblat’s PSP-SOI model. Read More...

Quartus gets under-the-hood reboot

Altera has released a new engine for its Quartus II software to scale up with the increasing density of large FPGAs. Read More...

Online portal speeds ASIC quotation process

To facilitate and improve the turnaround time for ASIC quotations, Open-Silicon has created a web portal for customers to submit their system requirements. Read More...

Fast extraction tool maintains high accuracy

Calibre xACT, a parasitic extraction platform from Mentor Graphics, provides attofarad accuracy and the ability to handle multimillion-instance designs to address a wide range of analog, digital, custom, and RF extraction requirements, including 14-nm FinFET. Read More...

Two-channel SMU sources and sinks

The GS820 source-measure unit from Yokogawa is available in 18 V and 50 V models. Read More...

Quantum computer kit announced – Save over $10,000,000!

The most exciting announcement this editor has ever covered: Quantum computing for the masses. Read More...

Xpedition Package Integrator spans IC chip to package to PCB

Mentor's new Package Integrator allows co-design of chips, single- & multi-chip packaging, and PCB layout. Read More...

Innovus Implementation System claims up to 10× turnaround time reduction

Cadence's new Innovus Implementation System shows impressive speedups and PPA results. Read More...

GaN transistor boosts efficiency, power density

Transphorm is offering engineering samples of the TPH3205WS, a 600-V GaN transistor in a small 3-pin TO-247 package that delivers high-efficiency operation in 80 Plus Titanium-class power-supply and inverter applications up to 3 kW. Read More...

One-stop-shop from IC design to silicon tape out

CEA-Leti has launched the Silicon Impulse IC design competence centre, offering IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles. Read More...

Extensible processor IP offers up to 75% memory power and area savings

Xtensa LX6 and Xtensa 11 processors enable users to create innovative custom processor instruction sets with up to 25% less processor logic power consumption and up to 75% better local memory area and power efficiency. Read More...

Catapult 8 a major HLS upgrade

Calypto is calling Catapult 8 "third generation" high-level synthesis technology, and it supports both C++ and SystemC. Read More...

PXI module exercises and characterizes DIO channels

The GX5295 from Marvin Test Solutions lets you add 32 DIO channels with source/sink capabilities to an PXI instrument chassis. Read More...

FPGA boards under $100: Altera/Terasic DE0-Nano

A close look at the Cyclone IV-based $79 DE0-Nano FPGA devboard from Terasic. Read More...

EDN Hot 100 products of 2014: EDA Tools, IP & Memory/Storage

This section of EDN's Hot 100 Products of 2014 includes design automation tools and memory/storage products. Read More...

FPGAs said to be industry’s most secure

Microsemi's ultra secure SmartFusion2 SoC FPGAs and IGLOO2 FPGAs are claimed to have more advanced security features at the device, design and system levels than any other leading FPGA. Read More...

Tabula FPGA provides 100% observability

Tabula's DesignInsight technology has the potential to provide a step-function improvement in development time and cost. Read More...

100 GHz real-time oscilloscope arrives

Teledyne LeCroy ups the oscilloscope bandwidth ante with the announcement of the LabMaster 10-100Zi. Read More...

Verification IP for 3D memory structures

Cadence Design Systems has announced verification IP supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube, High Bandwidth Memory, and DDR4 3D Stacking. Read More...

Memory IP targets low power requirements

In order to reach the stringent low power requirements of LCD drivers and touch screen controllers, Dolphin Integration has introduced a foundry-sponsored Single port RAM for the UMC 110 nm embedded Flash process. Read More...

MAX10 broadens the FPGA field

Altera's MAX series has graduated from CPLD to FPGA, and sports some unique features. Read More...

Audio analyzer claims world's lowest noise

Audio Precision's APx555 bridges the gap between bench and production testing while providing -117 dB of THD+N. Read More...

Mil temp-qualified FPGAs in 20-nm

Mil temp-qualified Arria 10 FPGAs and SoCs will allow military customers to make early specification decisions in designing avionics, radar and other high reliability applications, Altera says. Read More...

Cadence unveils Protium FPGA-based SoC prototyping platform

Protium puts two to eight Virtex-7 FPGAs under the hood to help you prototype & test complex SoCs. Read More...

NVM IP offers 75% area reduction

The non-volatile memory IP meets stringent automotive Grade 0 temperature and AEC-Q100 quality requirements. Read More...

Quantus QRC tears through extractions

Cadence's update to QRC, Quantus QRC, makes full use of your expensive server hardware, and can speed through extraction five times faster. Read More...

FPGA boards under $100: Introduction

I’m kicking off a major series of hands-on reviews of sub-$100 FPGA boards, so hop on “board” as we start our exploration. Read More...

iPad app from NI runs accurate SPICE simulations

Multisim Touch simulates circuit designs anywhere, anytime, says National Instruments; students, hobbyists and engineers can use the iPad app to design and simulate circuits using high-fidelity SPICE simulation with results identical to the desktop. Read More...

Path Finder mates PCB, IC package, & system design

The Xpedition Path Finder suite provides a single environment that gives cross-domain design teams the ability to model every device/interface. Read More...

IP for PHY connection to Hybrid Memory Cube is certified Compliant

Semtech's Snowbush family of 28-nm Platform Physical Layer IP offers support for the Hybrid Memory Cube specification for ultra fast, next-generation memory. Read More...

Dual-mode Soft IP core supports UART and FIFO operation

Digital Core Design has announced its D16950 soft IP core, featuring functional compatibility with the OX16C950 and an ability to support serial transmission in UART and FIFO modes. Read More...

I2C device interface IP for FPGA requires no programming

Digital Core Design has created DI2CSB -- an I2C slave base IP Core that doesn't need to be programmed. Read More...

Cypress adds entry-level chips to mixed-signal programmables

Expanding the PSoC 4 architecture with entry-level PSoC 4000 devices, Cypress has configured a family of low-cost ARM Cortex-M0 cores integrated with the CapSense, capacitive sensing system. Read More...

LPDDR4 IP offers 3200 Mbps performance

Synopsys LPDDR4 IP offering includes DesignWare LPDDR4 multiPHY, Enhanced Universal DDR Memory Controller and verification IP as well as hardening and signal integrity services Read More...

Streamline DDRx interface design with TimingDesigner/Sigrity melding

DDR design, especially DDR4, needs all the help it can get. Read More...

Companion FPGA packs 85K LUTs in 10x10mm package

The ECP5 FPGA Family was specifically designed to focus on key fast growing and high-volume markets such as small-cells, microservers, broadband access, or industrial video. Read More...

Software library enables FPGA-based drive control

The XSG AC Motor Control Library from software tool vendor dSpace speeds the development of Xilinx FPGA-based motor control designs. Read More...

Debugger teams with ARM’s System Trace Macrocell

Enhancements to Asset InterTech’s Arium hardware-assisted SourcePoint debugger optimize the processing of ARM’s System Trace Macrocell (STM), which provides developers of multicore, multithreaded SoCs a system-level perspective of trace data. Read More...

Software eases interconnect analysis of ARM-based SoCs

Interconnect Workbench from Cadence provides interconnect performance analysis and verification of SoC (system-on-chip) devices incorporating ARM CoreLink CCI-400, NIC-400, NIC-301, and ADB-400 system intellectual property (IP). Read More...

Hypervisor delivers security for multicore processors, enables multi-OS consolidation

Mentor Graphics has introduced an embedded hypervisor product for in-vehicle infotainment systems, telematics, advanced driver assistance systems, and instrumentation. Read More...

FastSPICE simulator offers up to 10X faster throughput

Cadence has introduced Spectre XPS (eXtensive Partitioning Simulator), featuring a breakthrough partitioning technology, that enables higher capacity and faster simulation while requiring two to three times less system memory. Read More...

Synopsys aims at TVs with ARC-based Dolby MS11 decoder

Synopsys' DesignWare IP for ARC Audio Processors has been augmented with support for Dolby Laboratories' Multistream Decoding, expanding the portfolio of ARC audio codecs. Read More...

System builder design tool targets ARM-based SmartFusion2 SoC FPGAs

Microsemi's System Builder is a new design tool within the Libero System-on-Chip (SoC) Design Environment version 11.0 and is specifically targeted at accelerating customer definition and implementation of ARM-based systems using SmartFusion2 SoC FPGAs. Read More...

FPGA/SoC families debut with performance boost, power reduction

Altera has announced its Generation 10 family comprising its Arria 10 and Stratix 10 series of FPGAs and SoCs. Read More...

Requirements lifecycle management tool targets safety-critical FPGA and ASIC design

Aldec's Spec-TRACER is a requirements lifecycle management solution for use in safety-critical industries in which rigorous certification standards exist; such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear. Read More...

Virtex 7-based FPGA module targets multi FPGA prototyping

Pro Design has added the proFPGA V7 mini FPGA module to its family of FPGA based prototyping solutions. Read More...

EDN Hot 100 products of 2012: EDA/IP and memory/storage

This section of EDN's Hot 100 Products of 2012 includes design automation software and memory/storage products. Read More...

NFC interface chip harvests energy from RF emissions

In addition to providing a contactless bridge between an NFC reader and any microcontroller, the AS3955 NFC interface tag IC from ams also acts as a power supply for the host device, harvesting as much as 5 mA at 4.5 V from the RF energy radiated by an NFC reader. Read More...

>> SEE ALL

1969 Compucorp calculator teardown

A 1969 scientific calculator teardown. This one's got them newfangled ICs. Read More...

Teardown: 1966 Programmable scientific calculator

Look inside a mid-1960s programmable scientific calculator! Read More...

Integration amassed: analyzing a NAS

This hands-on project showcases the second generation of Western Digital's My Book World Edition NAS (network-attached storage) device, so named because it is potentially accessible by a user from anywhere in the world. Read More...

One sensor does the work of many

The single-array camera captures images that conventionally require an array of sensors. Read More...

Inside the Schick Hydro microcontroller-powered wet razor

Though the shaving experience may be overrated, a look inside the Schick Hydro reveals another unexpected application for microcontrollers—in this case a less-than-$1 PIC10F222 from Microchip. Read More...

Artificial cochlea: an example of structural processing

Prying Eyes: A MEMS-based artificial cochlea mimics the real thing in form and function. Read More...

TV peripheral encompasses superset processor

Prying Eyes looks inside the Delkin eFilm Picturevision, which enables the playback of audio, still-image, and video files on a variety of memory-card formats. Read More...

Teardown: The nuances of variable-frequency drives

Get an inside view of induction-motor control by varying frequency using PWM. Read More...

>> SEE ALL

A Case Study - RF ASIC Validation of a satellite transceiver

ASIC validation in the RF world comes with its own set of hurdles and challenges, with high quality lab equipment, experience and know-how essential. A recently completed RF sub-system validation at S3 Group is presented in the form of a case study of the execution. The validation PCB design focussed on impedance matching and shielding RF signals from noise sources. We built up an efficient, automated test harness based on LabVIEW, MATLAB and python. This unified test framework facilitated instrument set-up, test-case running, data collection, traceability, plotting of measurements, waveform generation and analysis. Read More...

Matrix-based clock verification uncovers SoC bugs

Using the matrix based clock verification approach, we were able to cover corner-case scenarios and find about twenty critical design bugs across three SoCs. Read More...

Reverse bias techniques for high-end automotive microcontrollers & low leakage

A reverse-bias technique to reduce leakage, especially at high temperature (e.g., automotive). Read More...

The 7 levels of IP verification

IP quality should lead your list of SoC requirements. Here’s how to assess it. Read More...

Three ways the 3-terminal resistor model improves power converter circuits

Change the way power MOSFETs are modeled to increase the odds of first-pass power IC design success. Read More...

Mixed-mode verification of DDR, LCD, and memory sub-systems: Verilog-AMS vs. SPICE

Third in a series of mixed-mode verification articles, this installment covers memory and LCD interfaces. Read More...

Security architecture for automotive microcontroller flash memory

Read about various ways flash memory can be secured against malicious or accidental modification. Read More...

Verilog-AMS vs. SPICE view: An SoC verification comparison

It is important to weigh the pros and cons of a Verilog/Verilog-AMS view versus a SPICE view for all the analog blocks and IPs within a SoC. Read More...

A single misplaced atom can cause a system failure

Inside a semiconductor, a single atom deposited in the wrong place can cause the device to fail. Failure analysis and inspection can uncover the failure. Read More...

Robust asynchronous-reset architecture for scan coverage

Various scenarios, and the test architecture to robustly detect scan coverage – including potential race conditions – on asynchronous paths. Read More...

Validating MEMS and other sensors

Sensor validation requires a thorough blend of environmental, mechanical, and electrical techniques. Read More...

Product How-to: Fully utilize TSMC’s 28HPC process

Five logic library capabilities that give you bang for the buck in TSMC’s latest 28nm process. Read More...

Altera’s new Power Management team kicks it into high gear

Who would know how to optimally power Altera FPGAs better than their own power management team? Read More...

LTE-A Release 12 transmitter architecture: analog integration

In part 2 of a series, Damian Anzaldo explains how LTE-Advanced Release-12 shapes eNode transmitter architecture, specifically in terms of the analog integration challenge. The article includes an example using a MAX5868 RF DAC transmitter from Maxim Integrated. Read More...

RTL coding architecture affects power estimation & analysis

Small changes in RTL architecture can lead to big changes in power consumption. Read More...

Handle SEUs with C-slow retiming

Using C-Slow Retiming to generate a time-redundant digital design results in significantly reduced area and less power consumption, as compared to traditional techniques. Read More...

What’s stopping pre-silicon emulation from covering the last mile?

It has become essential to have a well-defined pre-silicon emulation platform, along with SoC verification, to find all design faults early in the cycle. Read More...

Test Memories at-speed with a slow clock

You may think that testing memory with a low-speed clock would miss many errors, but that's not the case. Read More...

Time for multimedia SoCs to get their analog signals right

As more and more analog I/O gets integrated onto SoCs, make sure you properly understand A/V signal characteristics and processing methods. Read More...

Interconnect (NoC) verification in SoC design

Use a “socket” concept to decouple IP cores from SoC busses. Read More...

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DesignCon 2016 opens call for papers

It’s time to sharpen your virtual pencils and submit your ideas for next year’s DesignCon. If your work concerns signal integrity, power integrity, or the interference between the two in high-speed designs, then DesignCon is the conference for you to show your work and get the feedback of your peers. Read More...

VCS commands ease coverage efforts & speed simulation

By using certain functions and commands in SystemVerilog and the Synopsys VCS tool, one can reduce coverage closure effort as well as the resultant simulation time. Read More...

A SystemC-based UVM verification infrastructure

TVS has made a SystemC library to enable UVM verification to be performed using SystemC rather than System Verilog freely available. Read More...

ARM TechCon opens call for proposals

Proposals now being accepted for ARM TechCon 2015, which will take place November 10-12, 2015 Read More...

Kintex-7, SEU mitigation using an isolated-design flow, part 1

Replicating and isolating redundant logic blocks within an FPGA fabric offers the potential of fault-tolerant implementation, confining SEUs to a single module preventing their propagation. Read More...

Improving analog design verification using UVM

Use UVM (universal verification methodology) to improve verification of AMS SoCs. Read More...

FinFET impact on dynamic power

FinFET-aware design implementation and effective dynamic power control throughout the flow is critical to unleash the full potential of these 3D devices. Read More...

18 Views of ISSCC

The latest and greatest chip R&D from ISSCC. Read More...

Security needs more than checklist compliance

Following a checklist of requirements is only a start for designing security into electronics products. Read More...

Entering the era of 3D printed electronics

A new development in 3D printing and conductive inks make 3D printed electronics a reality that will revolutionize electronics manufacturing starting this year. Read More...

Silicon debug challenges and guidelines

Guidelines for faster, more effective diagnosis during silicon debug. Read More...

A powerful power integrity workshop

A DesignCon'15 tutorial covers power integrity & PDN design in-depth. Read More...

Moore's Law extends to cover human progress

Moore's Law comes from the way people work and we can derive Moore’s-like laws for almost any developing technology or human endeavor. Read More...

Advanced fault models in small-scale CMOS technology nodes

Conventional tests fail at advanced CMOS nodes. More advanced fault models must be considered. Read More...

No glitter, games, or gimmicks, please

Trade show exhibits should stick to the technical and spare us the distractions. Read More...

Guidelines improve test quality in advanced CMOS nodes

IC test strategies to avoid false positives and improve yields. Read More...

Get a taste of SPICE at DesignCon

Every engineer needs easy access to a SPICE simulator tool. Get introduced to possibly the world's best SPICE tool at a DesignCon speed training event. Read More...

Vote for the Engineer of the Year

DesignCon2015 has announced the finalists for the Engineer of the Year Award (sponsored by National Instruments). The award includes a $10,000 grant that will be given out at DesignCon. Read More...

Design for test boot camp, Part 4: Built-in self-test

Built-in self-test is more than just test. It includes repair of failed circuits. Read More...

Clock monitors in SoC verification

Save time verifying clocks in complex IC designs. Read More...

Low power design – A case for RTL power analysis II

A look at the inaccuracies in RTL power analysis. Read More...

Design for test boot camp, part 2: Test compression

Test compression adds a small amount of circuitry for test purposes and drastically reduces test time while maintaining test coverage. Read More...

Multiple clock domain SoCs: Verification techniques

The authors discuss their experiences and share hints for the tools they use to verify complex designs. Read More...

Multiple clock domain SoCs: Addressing structural defects

The einfochips authors continue their in-depth look at multiple-clock domain designs. Read More...

>> SEE ALL

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