Verification methodology for low power: your blueprint to working silicon
The widespread design of energy-efficient mobile devices, desire for green power, and government regulations on idle power have created a powerful market force for the pervasive employment of design techniques for reducing power. Voltage-control techniques have emerged as the most popular and effective means to reducing power.
Conventional verification tools and methodologies don’t comprehend the impact of multiple operating voltages and fail to detect bugs that can manifest in silicon, some of which may lead to catastrophic failures. In the past couple of years, vendors of commercially available verification tools have responded to the challenge by changing the architecture of verification solutions to make them voltage-aware. However, verification methodology has not kept pace with the changing verification environment, and there is now a need for such a methodology to take advantage of the new tools. The combination of voltage-aware verification tools and a verification methodology specific to low power will dramatically improve the chances for first-pass working silicon for low-power designs.
Low-power world without verification methodology
Design teams grappling with compressed schedules and competitive pressures have been struggling without a structured, reusable, and scalable verification methodology for low power. When the choice is a delayed product launch versus comprehensive verification of a design, the absence of a documented verification methodology leads almost always to taping out the product with limited verification and hoping that there are no fatal power-management bugs. Some design teams even brazenly admit that they have planned for two to three re-spins for their designs when it comes to low-power applications because comprehensive verification of these designs is too time-consuming without a systematic approach to verification. Without a codified, well-understood, repeatable methodology, verification teams within the same company have their own ad hoc schemes to tackle verification complexity. Due to a lack of shared understanding of the root cause of these bugs and a methodology to detect and fix them before they manifest in silicon, the same design bugs are repeated in multiple designs from different design teams.
Verification methodology is a must-have for low-power designs
Many semiconductor companies designing low-power ICs have reached the conclusion that the lack of a verification methodology is a bottleneck to delivering upon their product road maps. Verification methodology has surfaced as a critical must-have for them to ensure their engineering success. Such a methodology has the potential to reduce overall verification effort, streamline the verification process to achieve high product quality, and build a repeatable and well-understood infrastructure for deployment across design teams within a company.
Elements of low-power verification methodology
Low-power bugs are not well-understood. After all, the functionality of a design doesn’t change because of design for low power. Power is a specification that has to be met, and different (often complex) design techniques are deployed to achieve this. RTL designers who design blocks of logic seldom deal with power-management techniques. The SoC designer or architect partitions the design into different power domains to meet the power budget of an IC and then introduces design elements to make this happen. This results in design bugs that are not very well-understood. Therefore, any low-power verification methodology must first educate designers and verification engineers on common causes of low-power bugs and how to detect them or, better yet, avoid them. A well-documented verification methodology on low power should list a number of rules, recommendations, and suggestions based on industry best practices for low-power designs.
Verification complexity explodes with the increasing complexity of low-power design techniques. The power-state space grows exponentially as the SoC architect increases the number of power domains in a low-power application. Verification engineers must now contemplate how to set up the power specification for the design. Factors that must be considered include: whether the power specification itself is bug-free; how to create a test plan for exercising the low-power features to ensure correct operation in silicon; what must be monitored during simulation; and how to track the overall progress of low-power verification. Verification teams also must be comfortable with the amount of static versus dynamic verification that they employ to check a design. A good verification plan must be designed with full knowledge of the possible failures of low-power design techniques and in a way that completely exercises the functionality of the design to confirm correct operation. Verification methodology for low power must advise on all these aspects based on accumulated verification experience from real designs.
Reusable verification infrastructure
Low-power verification can quickly become intractable with design complexity growth. To get a measure of this, a design with four power domains may have 16 power states to be verified, while a design with 20 power domains potentially requires verification in 1 million power states. Each power domain may have any number of power states, though not every combination of domains and states is necessarily valid or possible. Verification methodology is required to smartly reduce the verification-state space to a minimum set of power states that will provide complete verification coverage. A proper verification methodology should allow reuse of the existing all-on verification infrastructure to verify low-power features. It must also address verification of the large firmware component of power management.
Lessons learned from verifying one design need to be transferred to another design to minimize the amount of time required to complete verification runs. A verification environment that has been established for one design should be leveraged for another design. A well-written verification methodology is required to enable verification environment replication and reuse. In addition, standard software base classes should be part of such a verification methodology to help companies rapidly create a verification environment from scratch.
Adopting a verification methodology for low power can shave months from the verification process or even help debug a failed low-power design. The industry needs a well-documented verification methodology to reign in slipping low-power design schedules. Such a methodology must incorporate real design verification experience from low-power industry leaders. The presence or absence of a low-power verification methodology can mean the difference between first-pass silicon success or silicon failures. With so much riding on comprehensive verification of low-power designs, you can no longer afford to ignore low-power verification methodology.