Taking a bite out of power: techniques for low-power-ASIC design
By Michael Santarini, Senior Editor - May 24, 2007
Until recently, low-power-digital-IC design has been an area for specialist or guru IC designers. However, most IC-design engineers will have to learn a variety of low-power-design techniques as ASICs and SOCs (systems on chips) increasingly target processes of 130 nm and below. At 130-nm processes, foundries started to employ new techniques and materials, such as low-k dielectrics and copper, in silicon processes to increase design performance. However, smaller geometries, scaled thresholds, and unscaled voltages produced smaller, speedier ICs but produced a nasty side effect: leakage, or static power. By the 90-nm node, power management started to become a huge concern, and, at the 65-nm node, low-power-design techniques are a must.
“As we scale technology nodes, clearly we have to lower VDD [supply voltage], because there is a quadratic relationship: The power dissipation is proportional to VDD2,” says Mike Keating, a fellow at Synopsys. “If we just scaled the devices and did not scale VDD, we’d be doubling the power density every generation. We can’t do that, so we’ve been lowering VDD.”
When the semiconductor industry lowered supply voltage over the last few nodes, each reduction also lowered the transistor threshold voltage, which keeps drain-to-source current at a level that allows ICs to charge their output capacitors and thus increase the performance of ICs in those nodes. However, as the industry further decreased threshold voltage at each node, it forced the subthreshold leakage to also increase at each node. “As we’ve been shrinking processes, the gate-oxide thickness is so skinny now, gate leakage is increasing exponentially,” says Keating. “Somewhere around 65 and 45 nm, you end up with dynamic power equal to subthreshold current and equal to the gate-leakage current. We have a train wreck; only, in this case, we have three trains—dynamic power, subthreshold leakage, and gate leakage—headed to exactly the same spot.”
In the past, overall power density has essentially stayed the same for every process reduction. But, in 2005, the ITRS (International Technology Roadmap for Semiconductors) released a study that indicated that at the 65-nm node, dynamic-power density and leakage power would increase by 1.43 and 2.5 times, respectively. At the 45-nm node, the ITRS predicts, dynamic-power and leakage-power density will increase to two and 6.5 times, respectively. In reality, designs in high-speed 65-nm processes lose as much as half their power to leakage. Many in the industry believe that, by the 45-nm node, ICs will lose as much as 60% of their power to leakage (Figure 1). “Until recently, we’ve been dealing with power by simply making different trade-offs in silicon,” says Keating. “That option is sort of disappearing. Using these design techniques is no longer an option; it is a requirement.”
To deal with power management, the electronics community is employing new low-power techniques and materials on several fronts (Figure 2). Fabs have introduced multithreshold, multivoltage transistors; SOI (silicon-on-insulator) and low-k materials; body, or “back, biasing; and copper-metal and SiGe (silicon-germanium) substrates. Meanwhile, chip architects and software designers deal with low power by performing smart-hardware-versus-software trade-offs; by implementing power-savvy operating systems, introducing more hibernation modes into system design; and by more selectively granting memory access. IC designers are also employing several techniques to lower the power of their designs. The most popular techniques for low-power design include multithreshold design, multivoltage design, clock gating, power-aware memories, and power gating.
Jerry Frenkil, chief technology officer, vice president, and general manager of Sequence Design’s Silicon Business Unit, notes that low-power design is all about reducing one or several parts of the power equation: Dynamic power plus leakage power equals the device’s overall power consumption. Dynamic power is the power a device consumes when a user is employing it for its intended purpose, and leakage power is the power that leaking transistors waste (Figure 3).
Custom and circuit designers over the years have employed several techniques to lower the power of their designs, according to Kurt Keutzer, a professor at the University of California—Berkeley, who is a co-author and editor of Closing the Power Gap Between ASIC & Custom: Tools and Techniques for Low Power Design (Reference 1), which is due out by the time the Design Automation Conference takes place this June. However, he says, the power consumption of today’s typical ASICs may be three to seven times that of custom ICs fabricated in process technology of the same generation. He and one of the book’s co-authors, David Chinnery, estimate that, by employing low-power-design techniques, users can improve energy efficiency of their ASIC designs by a factor of two to three. “The main finding is that ASIC designers are leaving a lot of power savings on the table,” says Keutzer.
But there’s no silver bullet in low-power design. “There are a lot of techniques … and different methods attack different portions of the power equation. They usually have some overhead of some sort,” says Frenkil, also a contributor to the book. “Some may have no overhead, others may affect you in area, and others may affect you in speed. One of the critical things about low-power design is understanding the impact of what you are facing and how you are going to deal with it.” Indeed, users will have to mix and match many of these techniques to come up with a low-power methodology that works for them.
About five years ago, when excessive power consumption became a problem, foundries started to offer libraries for low-power and high-speed design. For example, TSMC (Taiwan Semiconductor Manufacturing Co) offers a standard, or nominal, library; a high-speed library; and a low-power library, each having several types of cells. For instance, each of TSMC’s libraries includes low-threshold-voltage, high-threshold-voltage, and threshold-voltage-with-MTCMOS (multithreshold-CMOS) cells. Multiple-cell libraries help designers deal with both leakage and dynamic power. To deal with leakage power using multiple types of cells, designers today employ multithreshold design. “Because we’ve played so many games with VDD and VTH [threshold voltage], we can’t create one library that is going to work for an entire design, because you have designs that are speed-critical, and, for the areas that are not speed-critical, you want to reduce the leakage,” says Keating.
A multicell library typically comprises at least two sets of identical cells that have different threshold voltages. Those with higher threshold voltage are slower but have less leakage; conversely, the cells with lower threshold voltage are faster but leak. “It is a nonlinear relationship,” says Keating. “Conceding a little bit of speed, you get a very dramatic reduction in leakage.” Frenkil says that a high-threshold-voltage cell typically has 50% less leakage than a low-threshold-voltage cell with no bad side effects, such as area gain.
For most applications, designers typically use a low-threshold-voltage library for a first pass through synthesis to get maximum performance and meet timing goals. They then determine the critical paths in their design—that is, the path or paths in the design that require the highest performance. They then try to locate areas that don’t require low-threshold-voltage cells and swap out low-voltage cells for high-voltage cells to reduce overall power and leakage of the design. Frenkil notes that this approach represents the most common use of the multithreshold-design technique because most applications have timing as a first requirement, low-threshold-voltage libraries run faster through synthesis, and synthesis tools ultimately produce smaller design areas from these libraries. Synthesis tools tend to run longer and produce larger design areas when running heavy doses of high-threshold-voltage cells.
However, in some wireless-system applications, power is the main goal, and area increases are less of an issue. In those cases, some designers first run synthesis with high-threshold-voltage cells, find the critical path, and then swap out the high-voltage cells with low-voltage cells until they reach their performance goal.
Although multithreshold design helps engineers minimize leakage of their designs through the use of multiple libraries, another technique, multivoltage design, helps designers control dynamic power. Similar to multithreshold design, multivoltage design enables designers to give the critical paths and blocks in their designs access to maximum voltage for the process and specification, but the designers then reduce the voltage for less power-hungry blocks. For example, Keating says, a processor block may require a clock speed of 500 MHz, but a USB core may require only 30 MHz to comply with the USB protocol and thus require less voltage to run. So, if designers give the USB core only the power it needs, they can drastically reduce the overall power the design consumes. To implement the method, designers traditionally put level shifters between blocks that are running at different voltages. “If you have a 0.9V region on your IC design that is sending a signal to a 1.2V region, you have to put a level shifter between the two regions so you can boost it to the swing in voltage and control timing,” Keating says.
Although a fairly simple concept, its implementation is more complex. First, designers must get used to dealing with multiple voltages on a die. “We are really trained as engineers that a chip has just one power supply, and now you have to deal with some complications,” says Keating. There are also some fairly significant challenges on the tools front. Most commercial synthesis and physical-design tools can insert level shifters and can perform multivoltage, but creating RTL is a problem. “HDLs don’t yet have a mechanism for describing power connectivity,” says Keating. This lack is one area that EDA vendors are addressing by trying to implement a low-power standard. Unfortunately, the industry players have diverged between two similar standards (see sidebar“EDA industry quibbles over power standards”).
Another emerging method that started in custom design but is making its way into ASIC design is the use of parallelism along with voltage scaling. In their book, Chinnery and Keutzer describe this technique. Keutzer says that people at first dismissed it as impractical but that it is now getting serious attention. “You parallelize to get the performance up and then scale voltage down to reduce the power and energy,” says Keutzer. “If you look at dynamic power, voltage is clearly where the biggest gains will be. So, how do you get the voltage down? Given a timing constraint—2 nsec, for example—you first overachieve your timing objective. In particular, you add parallelism to get the critical path down to 1.2 nsec. Then, you can scale down the voltage to relax back to the 2-nsec cycle time you need to achieve. The decrease in voltage more than compensates for the increase in area.”
Probably the oldest and most tried-and-true technique for reducing power is clock gating. One-third to one-half of an IC design’s dynamic power is in the chip’s clock-distribution system. “It’s a pretty simple concept: If you don’t need a clock running, shut it down,” says Keating. Today, the two popular methods of clock gating are local and global (Figure 4). If you feed old data to the output of a flip-flop back into its input through a multiplexer, you typically need not clock again. Therefore, you can replace each feedback multiplexer with a clock-gating cell that clocks the signal off. You would then use the enable signal that controls the multiplexer to control the clock cell to clock the signal off.
In the old days of digital design, designers had to manually perform this task, but any commercial synthesis tool worth its salt can now automatically do it. “The tools are all set up for that now, so they will go in, automatically look for multiplexers, and, if there is a feedback multiplexer, they’ll replace it with a clock-gating cell,” says Keating. “When you start talking about 32-bit registers, you can get significant savings using this technique.” He notes that Intel engineers this year presented a paper at SNUG (Synopsys Users Group) that reported a 43% savings in dynamic power using the technique (Reference 2).
The other popular approach of clock gating, global clock gating, is to simply turn off the clock to the whole block, typically from a central-clock-generator module. This method functionally shuts down the block, unlike local clock gating, but even further reduces dynamic power because it shuts down the entire clock tree.
Another popular technique for lowering both dynamic power and leakage is to use power-aware memories.
In its simplest form, the technique involves shutting down segments of a memory array when they are not in use. Another technique in this category is body-biasing memories. In this method, designers reverse-bias a memory when it is not in use, which essentially raises the threshold voltage and in turn slows leakage. Another technique gaining popularity is to use multimode power for memories. In this technique, designers employ memory with several power modes. Many designs employ dual-function memories so that, when the CPU accesses a memory to read or write data to run a main application, the memory receives full access to power to perform the operation. However, when the memory is not required to read or write, designers can program the memory to power down to a level at which the memory gets only enough power to retain its memory content.
Perhaps the hottest new methods for low-power design are power gating and MTCMOS (Figure 5). Like voltage gating, power gating involves temporarily shutting down blocks in a design when the blocks are not in use. And, like voltage gating, the technique is complex. “The neat thing about the other techniques is that they are pretty much all transparent to the design engineer,” says Keating. “When I’m writing my RTL, I don’t have to think about multithreshold, multivoltage, clock gating, or power-aware memories because someone else downstream has to worry about it. But with power gating, I have to worry about it at the RTL. I have to design a power controller that is going to control what blocks I need to shut down and when, and I have to think about what voltage I’m going to [need to] run different blocks.”
Traditionally, two methods for power gating are fine-grained and coarse-grained. In fine-grained power gating, designers place a switch transistor between ground and each gate. This approach allows designers to shut off the connection to ground whenever a series of functions is not in use. “You do that [technique] with every cell in the library,” says Keating. “At first, people really liked fine-grained power gating because it is fairly easy to do power characterization of each cell, but the problem is the area hit is very significant: two to four times larger.” Designers can also mix and match cells, having some power-gated and others not. Cells with high threshold voltage need not use power gating. For the most part, the power penalty is just too large, and many design groups are instead using coarse-grained power gating, in which designers create a power-switch network—essentially, a group of switch transistors that in parallel turn entire blocks on and off. The technique does not have the area hit of the fine-grained technique but is harder to characterize on a cell-by-cell basis.
Sequence Design’s Frenkil says that a compromise—medium-grained power gating—is also starting to emerge in the design community. In this method, he says, “Power-gating cells will power small blocks individually. … If you look at a high-performance, 65-nm process, the leakage can easily be 40 to 50% of your total power design. If you are designing a high-performance chip, you have to deal with an enormous amount of leakage, so people have several separate power domains controlled individually. I’ve seen one modestly sized chip that has 20 power domains; if you scale that up to a leading-edge chip, it will have over 100 power domains.” That number would be too hard to control with either a true fine-grained or a true coarse-grained technique. Of all the techniques, power gating has the most promise, says Frenkil. “It reduces leakage more, and it will scale well into the future, where things like back-biasing will not,” he says.
EDA vendors are feverishly attempting to automate the power-gating technique. The warring low-power standards, UPF (Unified Power Format) and CPF (Common Power Format), both aim to help design teams more effectively implement power-gating methods. Keating notes, for example, that, in UPF design, engineers still must design the power controller in RTL, but several tools help with the insertion of the power mesh, isolation cells, and retention registers into a design. “Instead of doing it in RTL, you can do it in a UPF command language and specify a certain number of blocks to be isolated,” says Keating. “In one line, you can do what it would take many lines of RTL to do. The tools are smart enough to take those commands and insert them at the appropriate levels. Some get inserted during synthesis; others get inserted during place and route.”
The method requires either manual or tool-automated insertion of isolation-retention flip-flops. “When you shut down a block, and its outputs go to a block that is still powered up, you have to worry about those power-down nodes floating, and they can float to the threshold voltage and create unwanted currents downstream,” says Keating. “You have to put isolation cells on those outputs and clamp that output to a one or a zero, so nothing gets hit by a floating current downstream.”
The method also requires the use of retention flip-flops. Keating notes that one of the problems with shutting down a block is that the block needs to restore or maintain all its states. To achieve this goal, designers can use retention flip-flops, in which the main part of the flip-flop has a low threshold voltage—that is, fast but leaky—and it sits beside a balloon register of high-threshold-voltage, low-leakage cells. “Just before you shut down a block, you put the output of the flip-flop into a balloon register,” says Keating. “Then, everything but the balloon register gets powered down to maintain the states. When the block powers back on, the balloon register dumps everything back on the main flip-flop, which helps quickly power the block up.”
EDA to the rescue?
Frenkil notes that, although EDA vendors offer a wide range of tools to help designers implement low-power-design techniques, the EDA industry also offers power-integrity tools to help designers consider the effects of design decisions on power. Power-integrity tools perform voltage-drop analysis, voltage-derated timing analysis, noise-margin analysis, and power-bus sizing. Many vendors offer low-power tools to attack the problem from every angle (Table 1). According to Keutzer, the EDA industry has yet to adequately address some problems. For example, the industry could provide tools that ease ASIC designers’ ability to implement microarchitecture techniques, such as pipelining; to more efficiently lay out clock networks; and to more effectively use transparent latches. However, he notes, no EDA tool can solve everyone’s power problem “It’s not about home runs; rather, it’s about a lot of singles,” says Keutzer.
Designers must become familiar with a mix of low-power-design techniques and should also investigate which tools will help them achieve their power goals. The EDA industry is trying to market a healthy field of tools to help designers control power. Eventually, vendors hope to provide design flows to allow designers to make trade-offs among timing, power, signal integrity, and, eventually, even thermal analysis (Reference 3). Top semiconductor companies, design houses, and EDA players are trying to establish a common power format. Even with the current field of EDA tools and the rough beginnings of integrated low-power flows, however, the EDA industry still has much work to do before it can solve the power problem.
|Company||Tool/starting price||Tasks||Where used in flow?||Description|
|Apache Design||RedHawk-LP/$95,000||Analysis||Postlayout (DEF/GDS)||Low-power-design analysis and optimization tool, including rush-current and ramp-up analysis, full-chip mixed-mode verification, and switch optimization for MTCMOS designs|
|RedHawk-ALP/$150,000||Analysis||Postlayout (DEF/GDS)||Extends RedHawk-LP to include ultralow-leakage-design techniques, such as substrate back-biasing (VTCMOS), power-gated memories, and on-chip low-dropout voltage regulators|
|ArchPro Design Automation||MVSim/NA||Analysis and verification||RTL, gate level||Cosimulator that simulates multivoltage effects with electrical accuracy; users can identify multivoltage issues using automatic assertion generation and analyze coverage of multivoltage states|
|MVRC/NA||Analysis and verification||RTL, gate level||Vectorless verification of multivoltage issues; users can detect topological, functional, and sequential issues with respect to power-management control|
|MVSyn/NA||Design||RTL, gate level||Automatic insertion of level shifters and isolation cells at RTL and gate level; users can perform electrically accurate simulations at the RTL/gate level with the inserted cells|
|Atrenta||Spyglass-Power/$60,000||Analysis||RTL, postsynthesis, after place and route||Provides a comprehensive approach to low-power design; helps manage power and voltage domains|
|Azuro||PowerCentric/NA||Design and analysis||Gate level, postphysical||Operates as a complete replacement for clock-tree synthesis within digital-design flows, comprehensively addressing power, timing, and variability within one unified optimization environment|
|Bluespec||ESEComp/$25,000||Design||ESL, RTL||Synthesizes SystemC designs into highly efficient Verilog RTL; enables rapid architectural exploration; accelerates the correct implementation of multiple clock domains, clock synchronizers, and gated clocks|
|BSC/$25,000||Design||ESL, RTL||Synthesizes Bluespec SystemVerilog designs into highly efficient Verilog Design; Bluespec's synthesis tools enable rapid architectural exploration and accelerate the correct implementation of multiple clock domains, clock synchronizers, and gated clocks|
|Cadence Design Systems||Cadence Low-Power Solution/NA||Design and analysis||RTL, gate level, transistor level||Integrates logic-design, verification, and implementation technologies with the Si2 CPF; reduces risk; improves productivity; achieves superior trade-off among timing, power, and area requirements|
|Encounter RTL Compiler global synthesis/NA||Design and analysis||RTL, gate level||Performs top-down multiobjective, multidomain, multimode synthesis for exploration and synthesis of multiple threshold voltages, multiple supplies, power shutoff, and voltage scaling, using CPF to sustain design intent|
|Encounter Conformal Low Power/NA||Analysis||RTL, gate level, transistor level||Verifies and debugs power-optimized multimillion-gate designs using CPF and combining low-power structural and functional checks with equivalence checking for superior performance, capacity, and ease of use|
|Encounter Test/NA||Design||Gate level||Creates test mode for each power domain, including shutoff requirements, as specified in CPF; inserts structures to control power during test; generates ATPG vectors that reduce power consumption during test|
|SoC Encounter/NA||Design and analysis||Gate-to-GDSII||Implements low-power designs; includes multiple-power-domain support for virtual prototyping, placement, and optimization; provides autoinsertion of low-power structures, such as switch cells and isolation cells; includes power-aware clock-tree synthesis, domain-aware routing, analysis of power consumption and IR-drop effects|
|Voltagestorm/NA||Analysis||Gate level||Integrates static- and dynamic-power-rail verification in CPF-enabled SoC Encounter; performs sign-off power analysis; automates analysis and optimization of decoupling capacitance size and location, resulting in lower dynamic-IR drop|
|Incisive Design Team and Enterprise Manager/NA||Verification||System level, RTL, gate level||Creates power plan and metrics in CPF-enabled flow; tracks power verification metrics against design and verification plan, ensuring full coverage-driven verification of all power-modes in the design|
|Incisive Design Team and Enterprice Simulator/NA||Verification||System level, RTL, gate level||Uses CPF for seamless verification of power shutoff without changing the verification environment; reduces risk of power-shutoff failure|
|Incisive Formal Verifier/NA||Verification||System level, RTL, gate level||Verifies power intent using standard assertion languages, complex power-control modules, and state and sequence relationships versus CPF specification; identifies corner cases without time-consuming simulation|
|Paladium III/NA||Verification||System level, RTL, gate level||Emulates system-level behavior, including both software and hardware, to quickly verify complex power-shutoff relationships|
|Xtreme III/NA||Verification||RTL, gate level||Reduces verification risk by seamlessly and rapidly verifying power shutoff without changing the RTL or verification environment|
|ChipVision Design Systems||Orinoco/$150,000||Design and analysis||Above RTL (system level)||Optimizes for low power at the electronic-system level to gain significant reduction of energy consumption|
|Golden Gate Technology||PowerGold/$250,000 per year list price||Power optimization||Postsynthesis physical design, gate level||Reduces power by 10 to 20% or more without impacting timing and complementing Cadence, Synopsys, or Magma flows|
|Magma Design Automation||Talus Power/NA||Design||RTL-to-GDSII||Enables optimal power management throughout the flow with power-aware synthesis, physical optimization, power-aware CTS, automated multivoltage, multiple threshold voltage, and MTCMOS methodology, allowing designers to minimize power and ensure uniform power distribution|
|Quartz Rail/NA||Analysis||RTL-to-GDSII||Analyzes power-integrity sign-off for power, IR drop, and thermal effects with a built-in SPICE engine for accurate results|
|Mentor Graphics||Questa 6.3/TBD||Analysis||RTL, gate level||Simulates power shutdown and power-up of power domains; provides voltage scaling to reduce power gating and retention behavior in designs|
|0-In CDC/TBD||Analysis||RTL||Uses clock gating to reduce dynamic-power consumption; ensures the design has no clock-domain-crossing issues|
|Sequence Design||PowerTheater/$115,000||Design and analysis||RTL, gate level||Provides RTL power analysis and management with silicon-aware features for voltage islands, multiple threshold voltages, power gating, and clock gating|
|CoolTime/$130,000||Analysis||Physical design||Provides dynamic voltage-drop analysis and optimization; analyzes timing, signal integrity, static-IR drop, and electromigration; supports design techniques, such as voltage islands, multiple threshold voltages, power gating, and clock gating|
|CoolCheck/$80,000||Analysis||Physical design||Provides early power-grid debugging with a fast formal technique for finding missing vias, weak connections, and highly resistive current paths in the power grid|
|CoolPower/$240,000||Design and analysis||Postroute design closure||Provides automatic, concurrent optimization of leakage power, dynamic power, timing, and signal integrity, including multiple threshold voltages and MTCMOS power-gating optimizations|
|Synopsys||VCS/$36,750||Verification||RTL, gate level||Provides comprehensive functional verification with built-in testbench, coverage, assertion, and debugging technology; supports power-aware verification, including correct handling of retention registers, and power-up/power-down sequences|
|Leda/$14,945||Analysis||RTL, gate level||Provides programmable RTL design and coding-guideline checker and built-in checks for CDC, SDC, power, and test; provides more than 50 low-power checks, including insertion/location of level shifters and isolation cells and clock gating to turn off power regions|
|Design Compiler Ultra/$98,000||Design||RTL||Provides comprehensive RTL synthesis, delivering best productivity; includes power and test-aware Topographical Technology|
|Power Compiler (add-on to Design Compiler Ultra)/$50,470||Design||RTL, gate level||Provides complete power-management synthesis for achieving the lowest power design; supports multivoltage, MTCMOS power gating, multithreshold leakage and gate-level power optimization, clock gating, and operand isolation|
|DFT MAX (add-on to DFT Compiler)/$123,725||Design||Gate level||Provides power-aware adaptive-scan compression for test data and time reduction|
|IC Compiler/$757,050||Design and analysis||Gate level||Provides complete physical implementation, including hierarchical-design planning with automated power-network synthesis and analysis; provides single convergent flow from netlist to silicon with support for multivoltage designs, multithreshold leakage, low-power placement and CTS, and state-retention power gating|
|PrimeTime PX/$24,500||Analysis||Gate level, TTL||Provides concurrent timing, signal integrity, and power analysis|
|PrimeRail/$176,645||Analysis||Gate level, TTL||Offers power-integrity sign-off with full-chip dynamic-power-integrity tool; provides cell- and transistor-level dynamic-voltage-drop and electromigration analysis|
|TetraMAX/$54,145||Analysis||Gate level||Offers power-aware manufacturing-test-pattern generation for designs incorporating scan design-for-test techniques, including compression|
|Innovator/$60,000||Preimplementation||Transaction (system) level||Provides software-driven power analysis and optimization with power-aware system software to measure the effects of architecture, power-management techniques, and software on power dissipation|
|EDA industry quibbles over power standards|
The EDA industry is responding to the challenges that designers face with power consumption. However, overcoming the low-power hurdle in a timely manner will likely require EDA vendors to collaborate on a common power format. Unfortunately, on the power front, the industry splits into two camps: A few small EDA companies back Cadence's CPF (Common Power Format), under the auspices of Si2 (Silicon Integration Initiative), whereas Synopsys, Mentor, and Magma back Accellera's UPF (Unified Power Format). Recently, it looked as if the two formats would merge under the IEEE, but politics in the industry have at least momentarily dashed the hope of that development. Ironically, those who have had access to both formats say that UPF and CPF share roughly 85% of the same functions. However, the EDA companies are guarding their formats in the hope that they will become de facto standards and thus be able to capture market share in a new tool area.
For now, it looks as though users and EDA vendors will have to support two formats. The industry and the designers have done it before with Verilog and VHDL—both viable HDLs (hardware-description languages). However, working with and supporting two formats create confusion, mistakes, delays, and more work for designers and vendors alike. One vendor notes that supporting two formats means that his company must allocate engineers to ensure that its tools support both formats. That requirement gives engineers less time to create tools to address tomorrow's challenges.